參數(shù)資料
型號： AM79C965KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁數(shù)： 59/220頁
文件大?。?/td> 1197K
代理商： AM79C965KCW
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P R E L I M I N A R Y
AMD
151
Am79C965
BCR1: Master Mode Write Active
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0 MSWRA
Reserved locations. After H_RE-
SET, the value in this register will
be 0005. The settings of this reg-
ister will have no effect on any
PCnet-32 controller function.
Writes to this register have no ef-
fect on the operation of the
PCnet-32 controller and will not
alter the value that is read.
BCR2: Miscellaneous Configuration
Bit
Name
Description
Note that all bits in this register
are programmable through the
EEPROM PREAD operation and
through
the
Software
Relo-
catable Mode operation.
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15
RES
Reserved location. Written and
read as zero.
14 T-MAULOOP
When set, this bit allows external
loopback packets to pass onto
the network through the T-MAU
interface, if the T-MAU interface
has been selected. If the T-MAU
interface has not been selected,
then this bit has no effect.
This bit is reset to ZERO by
H_RESET and is unaffected by
S_RESET or STOP.
13-9
RES
Reserved locations. Written and
read as zero.
8
IESRWE
IEEE Shadow Ram Write En-
able. The PCnet-32 controller
contains a shadow RAM on
board for storage of the IEEE ad-
dress
following
the
serial
EEPROM read operation. Ac-
cesses
to
APROM
I/O
Re-
sources will be directed toward
this RAM. When IESRWE is set
to a ONE, then 32-bit and 16-bit
write access to the shadow RAM
will be enabled.
When IESRWE is set to a ZERO,
then 32-bit and 16-bit write ac-
cess to the shadow RAM will be
disabled.
At no time are 8- bit write ac-
cesses to the shadow RAM
allowed.
This bit is reset to ZERO by
H_RESET and is unaffected by
S_RESET or STOP.
7
INTLEVEL
interrupt Level. This bit allows the
interrupt output signals to be pro-
grammed for edge or level-sensi-
tive applications.
When INTLEVEL is set to a
ZERO, the selected interrupt pin
is configured for edge sensitive
operation. In this mode, an inter-
rupt request is signaled by a high
level driven on the selected inter-
rupt pin by the PCnet-32 control-
ler. When the interrupt is cleared,
the selected interrupt pin is
driven to a low level by the
PCnet-32 controller. This mode
is intended for systems that do
not allow interrupt channels to be
shared by multiple devices.
When INTLEVEL is set to a ONE,
the selected interrupt pin is con-
figured for level sensitive opera-
tion. In this mode, an interrupt
request is signaled by a low level
driven on the selected interrupt
pin by the PCnet-32 controller.
When the interrupt is cleared, the
selected interrupt pin is floated
by the PCnet-32 controller and
allowed to be pulled to a high
level by an external pull-up de-
vice. This mode is intended for
systems which allow the interrupt
signal to be shared by multiple
devices.
This bit is reset to ZERO by
H_RESET and is unaffected by
R_RESET or STOP.
6-4
RES
Reserved locations. Written and
read as zero.
3
EADISEL
EADI Select. When set, this bit
configures three of the four LED
outputs to function as the outputs
of an EADI interface. LED1 be-
comes SFBD, LED2 becomes
SRDCLK and LEDPRE3 be-
comes SRD.
LNKST continues to
function as an LED output. In ad-
dition to these reassignments,
the INTR2 pin will be reassigned
to function as the
EAR pin.
This bit is reset to ZERO by
H_RESET and is unaffected by
S_RESET or STOP.
2
AWAKE
Auto-Wake. If LNKST is set and
AWAKE = “1”, the 10BASE-T re-
ceive circuitry is active during
sleep and listens for Link Pulses.
LNKST indicates Link Status and
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