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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 159/220頁 |
| 文件大小： | 1197K |
| 代理商： | AM79C965KCW |
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P R E L I M I N A R Y
AMD
43
Am79C965
LNKST
LINK Status
Output
This pin provides 12 mA for driving an LED. It indicates
an active link connection on the 10BASE-T interface.
The signal is programmable through BCR4. Note that
this pin is multiplexed with the EEDI function.
This pin remains active in snooze mode.
SHFBUSY
Shift Busy
Output
The function of the SHFBUSY signal is to indicate when
the last byte of the EEPROM contents has been shifted
out of the EEPROM on the EEDO signal line. This infor-
mation is useful for
external EEPROM-programmable
registers that do not use the microwire protocol, as is
described herein: When the PCnet-32 controller is per-
forming a serial read of the EEPROM through the
microwire interface, the SHFBUSY signal will be driven
HIGH. SHFBUSY can serve as a serial shift enable to
allow the EEPROM data to be serially shifted into an
external device or series of devices. The SHFBUSY
signal will remain actively driven HIGH until the end of
the EEPROM read operation. If the EEPROM check-
sum was verified, then the SHFBUSY signal will be
driven LOW at the end of the EEPROM read operation.
If the EEPROM checksum verification failed, then the
SHFBUSY signal will remain HIGH. This function effec-
tively demarcates the end of a successful EEPROM
read operation and therefore is useful as a programma-
ble-logic
low-active output enable signal. For more de-
tails on external EEPROM-programmable registers,
see the EEPROM.
Microwire Access section under
Hardware Access.
This pin can be controlled by the host system by writing
to BCR19, bit 3 (EBUSY).
SLEEP
Sleep
Input
When
SLEEP input is asserted (active LOW), the
PCnet-32 controller performs an internal system reset
and then proceeds into a power savings mode. (The
reset operation caused by
SLEEP assertion will not af-
fect BCR registers.) All outputs will be placed in their
normal reset condition. During sleep mode, all PCnet-32
controller inputs will be ignored except for the
SLEEP
pin itself. De-assertion of
SLEEP results in wake-up.
The system must refrain from starting the network op-
erations of the PCnet-32 controller for 0.5 seconds
following the deassertion of the
SLEEP signal in order to
allow internal analog circuits to stabilize.
Both BCLK and XTAL1 inputs must have valid clock
signals present in order for the
SLEEP command to
take effect.
If
SLEEP is asserted while LREQ/HOLD is asserted,
then the PCnet-32 controller will perform an internal
system reset and then wait for the assertion of
LGNT/
HLDA. When
LGNT/HLDA is asserted, the LREQ/
HOLD signal will be deasserted and then the PCnet-32
controller will proceed to the power savings mode. Note
that the internal system reset will not cause the
HOLD/
LREQ signal to be deasserted.
The
SLEEP pin should not be asserted during power
supply ramp-up. If it is desired that
SLEEP be asserted
at power up time, then the system must delay the asser-
tion of
SLEEP until three BCLK cycles after the comple-
tion of a valid pin
RESET operation.
XTAL1–XTAL2
Crystal Oscillator Inputs
Input/Output
The crystal frequency determines the network data rate.
The PCnet-32 controller supports the use of quartz crys-
tals to generate a 20 MHz frequency compatible with the
ISO 8802-3 (IEEE/ANSI 802.3) network frequency toler-
ance and jitter specifications. See the section
External
Crystal Characteristics (in section Manchester Encoder/
Decoder) for more detail.
The network data rate is one-half of the crystal fre-
quency. XTAL1 may alternatively be driven using an
external CMOS level source, in which case XTAL2 must
be left unconnected. Note that when the PCnet-32 con-
troller is in coma mode, there is an internal 22 K
resis-
tor from XTAL1 to ground. If an external source drives
XTAL1, some power will be consumed driving this resis-
tor. If XTAL1 is driven LOW at this time power consump-
tion will be minimized. In this case, XTAL1 must remain
active for at least 30 cycles after the assertion of
SLEEP
and deassertion of HOLD.
Microwire EEPROM Interface
EESK
EEPROM Serial Clock
Output
The EESK signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. This pin is
designed to directly interface to a serial EEPROM that
uses the microwire interface protocol. EESK is con-
nected to the microwire EEPROM’s Clock pin. It is con-
trolled by either the PCnet-32 controller directly during a
read of the entire EEPROM, or indirectly by the host
system by writing to BCR19, bit 1.
EESK can be used during programming of
external
EEPROM-programmable registers that do not use the
microwire protocol as follows:
When the PCnet-32 controller is performing a serial
read of the IEEE Address EEPROM through the
microwire interface, the SHFBUSY signal will serve as a
serial shift enable to allow the EEPROM data to be
serially shifted into an external device or series of de-
vices. This same signal can be used to gate the
output of
the programmed logic to avoid the problem of releasing
intermediate values to the rest of the system board logic.
The EESK signal can serve as the clock, and EEDO will
serve as the input data stream to the programmable
shift register.
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