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參數資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數： | 157/220頁 |
| 文件大小： | 1197K |
| 代理商： | AM79C965KCW |
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P R E L I M I N A R Y
AMD
41
Am79C965
If Multi-Interrupt mode has been selected and the daisy-
chain arbitration feature is not used, then the HOLDI
input should be tied to VSS through a resistor.
Note that this pin changes polarity when VL mode has
been selected (see pin description of
LREQI in VESA
VL-Bus Interface section).
INTR1–INTR4
Interrupt Request
Output
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDON, MFCO, RCVCCO, TXSTRT, or JAB. Each
of these status flags has a mask bit which allows for
suppression of INTR assertion. These flags have the
meaning shown in Table 16.
Table 16. Status Flags
BABL
Babble (CSR0, bit 14)
MISS
Missed Frame (CSR0, bit 12)
MERR
Memory Error (CSR0, bit 11)
RINT
Receive Interrupt (CSR0, bit 10)
IDON
Initialization Done (CSR0, bit 8)
MFCO
Missed Packet Count Overflow
(CSR4, bit 9)
RCVCCO
Receive Collision Count Overflow
(CSR4, bit 5)
TXSTRT
Transmit Start (CSR4, bit 3)
JAB
Jabber (CSR4, bit 1)
Note that there are four possible interrupt pins, depend-
ing upon the mode that has been selected with the
JTAGSEL pin. Only one interrupt pin may be used at
one time. The active interrupt pin is selected by pro-
gramming the interrupt select register (BCR21). The de-
fault setting of BCR121will select interrupt INTR1 as the
active interrupt. Note that BCR21 is EEPROM-program-
mable. Inactive interrupt pins are floated.
The polarity of the interrupt signal is determined by the
INTLEVEL bit of BCR2. The interrupt pins may be
programmed for level-sensitive or edge-sensitive
operation.
PCnet-32 controller interrupt pins will be floated at
H_RESET and will remain floated until either the
EEPROM has been successfully read, or, following an
EEPROM read failure, a Software Relocatable Mode
sequence has been successfully executed.
LDEV
Local Device
Output
LDEV is driven by the PCnet-32 controller when it recog-
nizes an access to PCnet-32 controller I/O space. Such
recognition is dependent upon a valid sampled
ADS
strobe plus valid M/
IO, D/C and A31–A5 values.
M/IO
Memory I/O Select
Input/Output
During slave accesses to the PCnet-32 controller, the
M/
IO pin, along with D/C and W/R, indicates the type of
cycle that is being performed. PCnet-32 controller will
only respond to local bus accesses in which M/
IO is
sampled as a zero by the PCnet-32 controller.
During PCnet-32 controller bus master accesses, the
M/
IO pin is an output and will always be driven high.
M/
IO is floated if the PCnet-32 controller is not the cur-
rent master on the local bus.
RESET
System Reset
Input
When RESET is asserted high and the LB/
VESA pin has
been tied to VDD, then the PCnet-32 controller performs
an internal system reset of the type H_RESET (HARD-
WARE_RESET). The RESET pin must be held for a
minimum of 30 BCLK periods. While in the H_RESET
state, the PCnet-32 controller will float or deassert all
outputs.
Note that this pin changes polarity when VL mode has
been selected (see pin description of
RESET in VESA
VL-Bus Interface section).
RDY
Ready
Output
RDY functions as an output from the PCnet-32 control-
ler during PCnet-32 controller slave cycles. During
PCnet-32 controller slave read cycles,
RDY is asserted
to indicate that valid data has been presented on the
data bus. During PCnet-32 controller slave write cycles,
RDY is asserted to indicate that the data on the data bus
has been internally latched.
RDY is asserted for one
BCLK period.
RDY is then driven high for one-half of one
clock period before being released.
RDY is floated if the PCnet-32 controller is not the cur-
rent slave on the local bus.
In systems where both
RDY and RDYRTN (or equiva-
lent) signals are provided,
RDY must NOT be tied to
RDYRTN. Most systems now provide for a local device
ready input to the memory controller that is separate
from the CPU
READY signal. This second READY sig-
nal is usually labeled as
READYIN. This signal should
be connected to the PCnet-32 controller
RDY signal.
The CPU
READY signal should be connected to the
PCnet-32 controller
RDYRTN pin.
In systems where only one
READY signal is provided,
then
RDY may be tied to RDYRTN.
RDYRTN
Ready Return
Input
RDYRTN functions as an input to the PCnet-32 control-
ler.
RDYRTN is used to terminate all master accesses
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