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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 139/220頁 |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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P R E L I M I N A R Y
AMD
25
Am79C965
is controlled by the EEPROM during reads. It may be
read by the host system by reading BCR19, bit 0.
EEDO can be used during programming of
external
EEPROM-programmable registers that do not use the
microwire protocol as follows:
When the PCnet-32 controller is performing a serial
read of the IEEE Address EEPROM through the
microwire interface, the SHFBUSY signal will serve as a
serial shift enable to allow the EEPROM data to be
serially shifted into an external device or series of de-
vices. This same signal can be used to gate the
output of
the programmed logic to avoid the problem of releasing
intermediate values to the rest of the system board logic.
The EESK signal can serve as the clock, and EEDO will
serve as the input data stream to the programmable
shift register.
EECS
EEPROM Chip Select
Output
The function of the EECS signal is to indicate to the
microwire EEPROM device that it is being accessed.
The EECS signal is active high. It is controlled by either
the PCnet-32 controller during a read of the entire
EEPROM, or indirectly by the host system by writing to
BCR19, bit 2.
EEDI
EEPROM Data In
Output
The EEDI signal is used to access the external ISO
8802-3 (IEEE/ANSI 802.3) address PROM. EEDI func-
tions as an output. This pin is designed to directly inter-
face to a serial EEPROM that uses the microwire
interface protocol. EEDI is connected to the microwire
EEPROM’s Data Input pin. It is controlled by either the
PCnet-32 controller during command portions of a read
of the entire EEPROM, or indirectly by the host system
by writing to BCR19, bit 0.
Attachment Unit Interface
CI
±
Collision In
Input
A differential input pair signaling the PCnet-32 controller
that a collision has been detected on the network media,
indicated by the CI
± inputs being driven with a 10 MHz
pattern of sufficient amplitude and pulse width to meet
ISO 8802-3 (IEEE/ANSI 802.3) standards. Operates at
pseudo ECL levels.
DI
±
Data In
Input
A differential input pair to the PCnet-32 controller carry-
ing Manchester encoded data from the network. Oper-
ates at pseudo ECL levels.
DO
±
Data Out
Output
A differential output pair from the PCnet-32 controller for
transmitting Manchester encoded data to the network.
Operates at pseudo ECL levels.
Twisted Pair Interface
RXD
±
10-BASE-T Receive Data
Input
10BASE-T port differential receivers.
TXD
±
10BASE-T Transmit Data
Output
10BASE-T port differential drivers.
TXP
±
10BASE-T Pre-distortion Control
Output
These outputs provide transmit predistortion control in
conjunction with the 10BASE-T port differential drivers.
External Address Detection Interface
The EADI interface is enabled through bit 3 of
BCR2 (EADISEL).
EAR
External Address Reject Low
Input
An EADI input signal. The incoming frame will be
checked against the internally active address detection
mechanisms and the result of this check will be OR’d
with the value on the
EAR pin. The EAR pin is defined as
REJECT.
See the EADI section for details regarding the function
and timing of this signal.
Note that this pin is multiplexed with the INTR2 pin.
SFBD
Start Frame–Byte Delimiter
Output
Start Frame–Byte Delimiter Enable. EADI output signal.
An initial rising edge on this signal indicates that a start
of frame delimiter has been detected. The serial bit
stream will follow on the SRD signal, commencing with
the destination address field. SFBD will go high for 4 bit
times (400 ns) after detecting the second “1” in the SFD
(Start of Frame Delimiter) of a received frame. SFBD will
subsequently toggle every 400 ns (1.25 MHz frequency)
with each rising edge indicating the first bit of each sub-
sequent byte of the received serial bit stream. SFBD will
be inactive during frame transmission.
Note that this pin is multiplexed with the LED1 pin.
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