參數(shù)資料
型號： AM79C965KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類： 微控制器/微處理器
英文描述： 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁數(shù)： 51/220頁
文件大?。?/td> 1197K
代理商： AM79C965KCW
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁當(dāng)前第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁
AMD
P R E L I M I N A R Y
144
Am79C965
INTEGER
portion
of
the
÷
operation.
Note: If either Linear Burst Write
is enabled, the value has to be
greater than or equal to 4.
Read/write accessible only when
the STOP bit is set.
CSR82: Bus Activity Timer
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0 DMABAT
Bus Activity Timer Register. If the
TIMER bit in CSR4 is set, this
register contains the maximum
allowable time that PCnet-32
controller will take up on the sys-
tem bus during FIFO data trans-
fers for a single DMA cycle. The
Bus Activity Timer Register does
not limit the number of transfers
during Descriptor transfers.
The DMABAT value is inter-
preted as an unsigned number
with a resolution of 0.1
s. For in-
stance, a value of 51
s would be
programmed with a value of 510.
If the TIMER bit in CSR4 is set,
DMABAT is enabled and must be
initialized
by
the
user.
The
DMABAT register is undefined
until written. When the ENTST bit
in CSR4 is set, all writes to this
register will automatically per-
form a decrement cycle.
If the user has NOT enabled the
Linear Burst function and wishes
the PCnet-32 controller to limit
bus activity to MAX_TIME
s,
then the Burst Timer should be
programmed to a value of:
MAX_TIME- [(11 + 4w) x (BCLK
period)],
where w = wait states.
If the user has enabled the Linear
Burst function and wishes the
PCnet-32 controller to limit bus
activity to MAX_TIME
s, then
the Burst Timer should be pro-
grammed to a value of:
MAX_TIME- [((3+lbs) x w + 10 +
lbs) x (BCLK period)],
where w = wait states and lbs =
linear burst size in number of
transfers per sequence.
This is because the PCnet-32
controller may use as much as
one “l(fā)inear burst size” plus three
transfers in order to complete the
linear burst before releasing the
bus.
As an example, if the linear burst
size is four transfers, and the
number of wait states for the sys-
tem memory is two, and the
BCLK period is 30 ns and the
MAX time allowed on the bus is
3
s, then the Burst Timer should
be programmed for:
MAX_TIME- [((3+lbs) x w + 10 +
lbs) x (BCLK period)],
3 ms - [(3 + 4) x 2 +10 + 4) x (30
ns)] = 3 ms - (28 x 30 ns) = 3 - 0.84
m
s = 2.16 ms.
Then, if the PCnet-32 controller’s
Bus ActivityTimer times out after
2.16
s when the PCnet- 32 con-
troller has completed all but the
last three transfers of a linear
burst, the PCnet-32 controller
may take as much as 0.84
s to
complete the bursts and release
the bus. The bus release will oc-
cur at 2.16 + 0.84 = 3
s.
A value of zero will in the
DMABAT
register
with
the
TIMER bit in CSR4 set to ONE
will produce single linear burst
sequences per bus master pe-
riod when programmed for linear
burst mode, and will yield sets of
three transfers when not pro-
grammed for linear burst mode.
The Bus Activity Timer is set to a
value of 00h after H_RESET or
S_RESET and is unaffected by
STOP.
Read/write accessible only when
STOP bit is set.
CSR84: DMA Address Lower
Bit
Name
Description
31-16
RES
Reserved locations. Written as
zeros and read as undefined.
15-0
DMABA
DMA Address Register.
This register contains the lower
16 bits of the address of system
memory for the current DMA cy-
cle. The Bus Interface Unit con-
trols the Address Register by
issuing increment commands to
increment the memory address
for sequential operations. The
DMABA register is undefined
相關(guān)PDF資料
PDF描述
AM80A-024L-120F18 1-OUTPUT 240 W DC-DC REG PWR SUPPLY MODULE
AJ80A-024L-033F50 1-OUTPUT 240 W DC-DC REG PWR SUPPLY MODULE
AM93LC66S 4096-bits Serial Electrically Erasable PROM
AM93LC66SA 4096-bits Serial Electrically Erasable PROM
AM93LC66VN 4096-bits Serial Electrically Erasable PROM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AM79C970 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus
AM79C970A 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
AM79C970AKC\\W 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述:
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*