- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄295065 > AM79C965KCW (ADVANCED MICRO DEVICES INC) 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 PDF資料下載
參數(shù)資料
| 型號(hào)： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 113/220頁(yè) |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)當(dāng)前第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)第193頁(yè)第194頁(yè)第195頁(yè)第196頁(yè)第197頁(yè)第198頁(yè)第199頁(yè)第200頁(yè)第201頁(yè)第202頁(yè)第203頁(yè)第204頁(yè)第205頁(yè)第206頁(yè)第207頁(yè)第208頁(yè)第209頁(yè)第210頁(yè)第211頁(yè)第212頁(yè)第213頁(yè)第214頁(yè)第215頁(yè)第216頁(yè)第217頁(yè)第218頁(yè)第219頁(yè)第220頁(yè)
AMD
P R E L I M I N A R Y
20
Am79C965
If
BRDY and RDYRTN are sampled active in the same
cycle, then
RDYRTN takes precedence, causing the
next transfer cycle to begin with a T1 cycle.
BRDY functions as an output during PCnet-32 controller
slave cycles and is always driven inactive (HIGH).
BRDY is floated if the PCnet-32 controller is not being
accessed as the current slave device on the local bus.
D/C
Data/Control Select
Input/Output
During slave accesses to the PCnet-32 controller, the
D/
C pin, along with M/IO and W/R, indicates the type of
cycle that is being performed. PCnet-32 controller will
only respond to local bus accesses in which D/
C is
driven HIGH by the local bus master.
During PCnet-32 controller bus master accesses, the
D/
C pin is an output and will always be driven HIGH.
D/
C is floated if the PCnet-32 controller is not the current
master on the local bus.
DAT0–DAT31
Data Bus
Input/Output
Used to transfer data to and from the PCnet-32 control-
ler to system resources via the local bus. DAT31–DAT0
are driven by the PCnet-32 controller when performing
bus master writes and slave read operations. Data on
DAT31–DAT0 is latched by the PCnet-32 controller
when performing bus master reads and slave write
operations.
The PCnet-32 controller will always follow Am386DX
byte lane conventions. This means that for word and
byte accesses in which PCnet-32 controller drives the
data bus (i.e. master write operations and slave read
operations), the PCnet-32 controller will produce dupli-
cates of the active bytes on the unused half of the 32-bit
data bus. Table 6 illustrates the cases in which duplicate
bytes are created.
Table 6. Byte Duplication on Data Bus
BE3–
DAT
BE0
[31:24]
[23:16]
[15:8]
[7:0]
1110
Undef
A
1101
Undef
A
Undef
1011
Undef
A
Undef
Copy A
0111
A
Undef
Copy A
Undef
1100
Undef
B
A
1001
Undef
C
B
Undef
0011*
D
C
Copy D
Copy C
1000
Undef
C
B
A
0001
D
C
B
Undef
0000
D
C
B
A
*Note: Byte duplication does not apply during a
LBS16
access. See Table 8.
INTR1–INTR4
Interrupt Request
Output
An attention signal which indicates that one or more of
the following status flags is set: BABL, MISS, MERR,
RINT, IDON, MFCO, RCVCCO, TXSTRT, or JAB. Each
of these status flags has a mask bit which allows for
suppression of INTR assertion. These flags have the
meaning shown in Table 7.
Table 7. Status Flags
BABL
Babble (CSR0, bit 14)
MISS
Missed Frame (CSR0, bit 12)
MERR
Memory Error (CSR0, bit 11)
RINT
Receive Interrupt (CSR0, bit 10)
IDON
Initialization Done (CSR0, bit 8)
MFCO
Missed Packet Count Overflow
(CSR4, bit 9)
RCVCCO
Receive Collision Count Overflow
(CSR4, bit 5)
TXSTRT
Transmit Start (CSR4, bit 3)
JAB
Jabber (CSR4, bit 1)
Note that there are four possible interrupt pins, depend-
ing upon the mode that has been selected with the
JTAGSEL pin. Only one interrupt pin may be used at
one time. The active interrupt pin is selected by pro-
gramming the interrupt select register (BCR21). The
default setting of BCR121will select interrupt INTR1 as
the active interrupt. Note that BCR21 is EEPROM-pro-
grammable. Inactive interrupt pins are floated.
The polarity of the interrupt signal is determined by the
INTLEVEL bit of BCR2. The interrupt pins may be
programmed for level-sensitive or edge-sensitive
operation.
PCnet-32 controller interrupt pins will be floated at
H_RESET and will remain floated until either the
EEPROM has been successfully read, or, following an
EEPROM read failure, a Software Relocatable Mode
sequence has been successfully executed.
LBS16
Local Bus Size 16
Input
BS16 is sampled during PCnet-32 controller bus mas-
tering activity to determine if the target device on the
VL-Bus is 32 or 16 bits in width. If the
LBS16 signal is
sampled active at least one clock period before the as-
sertion of
LRDY during a PCnet-32 controller bus mas-
ter transfer, then the PCnet-32 controller will convert a
single 32-bit transfer into two 16-bit transfers. Not all
32-bit transfers need to be split into two 16-bit transfers.
Table 8 shows the sequence of transfers that will be
executed for each possible 32-bit bus transfer that en-
counters a proper assertion of the
LBS16 signal.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM80A-024L-120F18 | 1-OUTPUT 240 W DC-DC REG PWR SUPPLY MODULE |
| AJ80A-024L-033F50 | 1-OUTPUT 240 W DC-DC REG PWR SUPPLY MODULE |
| AM93LC66S | 4096-bits Serial Electrically Erasable PROM |
| AM93LC66SA | 4096-bits Serial Electrically Erasable PROM |
| AM93LC66VN | 4096-bits Serial Electrically Erasable PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。