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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 121/220頁 |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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B-1
Am79C965
Recommendation for Power and
Ground Decoupling
APPENDIX B
The mixed analog/digital circuitry in the PCnet-32 make
it imperative to provide noise-free power and ground
connections to the device. Without clean power and
ground connections, a design may suffer from high bit
error rates or may not function at all. Hence, it is highly
recommended that the guidelines presented here are
followed to ensure a reliable design.
Decoupling/Bypass Capacitors: Adequate decoupling
of the power and ground pins and planes is required by
all PCnet-32 designs. This includes both low-frequency
bulk capacitors and high frequency capacitors. It is rec-
ommended that at least one low-frequency bulk (e.g.
22
F) decoupling capacitor be used in the area of the
PCnet-32 device. The bulk capacitor(s) should be con-
nected directly to the power and ground planes. In addi-
tion, at least 8 high frequency decoupling capacitors
(e.g. 0.1
F multilayer ceramic capacitors) should be
used around the periphery of the PCnet-32 device to
prevent power and ground bounce from affecting device
operation. To reduce the inductance between the power
and ground pins and the capacitors, the pins should be
connected directly to the capacitors, rather than through
the planes to the capacitors. The suggested connection
scheme for the capacitors is shown in the figure below.
Note also that the traces connecting these pins to the
capacitors should be as wide as possible to reduce in-
ductance (15 mils is desirable).
PCnet
Vdd
Vss
C
A
P
C
A
P
PCnet
Vdd
Vss
C
A
P
PCnet
Vdd
Vss
Via to the Power Plane
Via to the Ground Plane
Correct
Incorrect
The most critical pins in the layout of a PCnet-32 design
are the 4 analog power and 2 analog ground pins,
AVDD[1-4] and AVSS[1-2], respectively. All of these
pins are located in one corner of the device, the “analog
corner”. Specific functions and layout requirements of
the analog power and ground pins are given below.
AVSS1 and AVDD3: These pins provide the power and
ground for the Twisted Pair and AUI drivers. In addition
AVSS1 serves as the ground for the logic interfaces in
the 20 MHz Crystal Oscillator. Hence, these pins can be
very noisy. A dedicated 0.1
F capacitor between these
pins is recommended.
AVSS2 and AVDD2: These pins are the most critical
pins on the PCnet-32 device because they provide the
power and ground for the phase-lock loop (PLL) portion
of the chip. The voltage-controlled oscillator (VCO) por-
tion of the PLL is sensitive to noise in the 60 kHz –
200 kHz range. To prevent noise in this frequency range
from disrupting the VCO, it is strongly recommended
that the low-pass filter shown below be implemented on
these pins.
VDD plane
33
F to 10 F
AVDD2
AVSS2
PCnet
TM
1
to 10
VSS plane
To determine the value for the resistor and capacitor,
the formula is:
R * C
≥ 88
where R is in ohms and C is in microfarads. Some possi-
ble combinations are given below. To minimize the volt-
age drop across the resistor, the R value should not be
more than 10
.
2.7
33
F
4.3
22
F
6.8
15
F
10
10
F
RC
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