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參數(shù)資料
| 型號(hào)： | AM79C965KCW |
| 廠(chǎng)商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 161/220頁(yè) |
| 文件大小： | 1197K |
| 代理商： | AM79C965KCW |
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P R E L I M I N A R Y
AMD
45
Am79C965
Note that this pin is multiplexed with the LED1 pin.
SRD
Serial Receive Data
Output
An EADI output signal. SRD is the decoded NRZ data
from the network. This signal can be used for external
address detection. Note that when the 10BASE-T port is
selected, transitions on SRD will only occur during
receive activity. When the AUI port is selected, transi-
tions on SRD will occur during both transmit and re-
ceive activity.
Note that this pin is multiplexed with the LEDPRE3 pin.
SRDCLK
Serial Receive Data Clock
Output
An EADI output signal. Serial Receive Data is synchro-
nous with reference to SRDCLK. Note that when the
10BASE-T port is selected, transitions on SRDCLK will
only occur during receive activity. When the AUI port is
selected, transitions on SRDCLK will occur during both
transmit and receive activity.
Note that this pin is multiplexed with the LED2 pin.
General Purpose Serial Interface
The GPSI interface is selected through the PORTSEL
bits of the Mode register (CSR15) and enabled through
the TSTSHDW[1] bit (BCR18) or the GPSIEN bit
(CSR124).
Note that when GPSI test mode is invoked, slave ad-
dress decoding must be restricted to the lower 24 bits of
the address bus by setting the IOAW24 bit in BCR2 and
by pulling LED2 LOW during Software Reloactable
Mode. The upper 8 bits of the address bus will always be
considered matched when examining incoming I/O ad-
dresses. During master accesses while in GPSI mode,
the PCnet-32 controller will not drive the upper 8 bits of
the address bus with address information. See the GPSI
section for more detail.
TXDAT
Transmit Data
Input/Output
TXDAT is an output, providing the serial bit stream for
transmission, including preamble, SFD data and FCS
field, if applicable.
Note that the TxDAT pin is multiplexed with the A31 pin.
TXEN
Transmit Enable
Input/Output
TXEN is an output, providing an enable signal for trans-
mission. Data on the TXDAT pin is not valid unless the
TXEN signal is HIGH.
Note that the TXEN pin is multiplexed with the A30 pin.
STDCLK
Serial Transmit Data Clock
Input
STDCLK is an input, providing a clock signal for MAC
activity, both transmit and receive. Rising edges of the
STDCLK can be used to validate TXDAT output data.
The STDCLK pin is multiplexed with the A29 pin.
Note that this signal must meet the frequency stability
requirement of the ISO 8802-3 (IEEE/ANSI 802.3)
specification for the crystal.
CLSN
Collision
Input/Output
CLSN is an input, indicating to the core logic that a
collision has occurred on the network.
Note that the CLSN pin is multiplexed with the A28 pin.
RXCRS
Receive Carrier Sense
Input/Output
RXCRS is an input. When this signal is HIGH, it indi-
cates to the core logic that the data on the RXDAT input
pin is valid.
Note that the RXCRS pin is multiplexed with the A27 pin.
SRDCLK
Serial Receive Data Clock
Input/Output
SRDCLK is an input. Rising edges of the SRDCLK sig-
nal are used to sample the data on the RXDAT input
whenever the RXCRS input is HIGH.
Note that the SRDCLK pin is multiplexed with the
A26 pin.
RXDAT
Receive Data
Input/Output
RXDAT is an input. Rising edges of the SRDCLK signal
are used to sample the data on the RXDAT input when-
ever the RXCRS input is HIGH.
Note that the RXDAT pin is multiplexed with the A25 pin.
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| AM79C970 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
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| AM79C970AKC | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
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