參數(shù)資料
型號(hào)： AM79C965KCW
廠商： ADVANCED MICRO DEVICES INC
元件分類(lèi)： 微控制器/微處理器
英文描述： 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16
封裝： PLASTIC, QFP-160
文件頁(yè)數(shù)： 45/220頁(yè)
文件大?。?/td> 1197K
代理商： AM79C965KCW
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P R E L I M I N A R Y
AMD
139
Am79C965
CSR58: Software Style
Bit
Name
Description
This register is an alias of the lo-
cation BCR20. Accesses to/from
this register are equivalent to ac-
cesses to BCR20.
31-10
RES
Reserved locations. Written as
zeros and read as undefined.
9
CSRPCNET
CSR PCnet-ISA configuration
bit. When set, this bit indicates
that the PCnet-32 controller reg-
ister bits of CSR4 and CSR3 will
map directly to the CSR4 and
CSR3 bits of the PCnet-ISA
(Am79C960)
device.
When
cleared, this bit indicates that
PCnet-32 controller register bits
of CSR4 and CSR3 will map di-
rectly to the CSR4 and CSR3 bits
of
the
ILACC
(Am79C900)
device.
The value of CSRPCNET is de-
termined by the PCnet-32 con-
troller. CSRPCNET is read only
by the host.
The PCnet-32 controller uses the
setting of the Software Style reg-
ister
(BCR20[7:0]/CSR58[7:0])
to determine the value for this bit.
CSRPCNET is set to a ONE by
H_RESET or S_RESET and is
not affected by STOP.
8
SSIZE32
Software Size 32 bits. When set,
this
bit
indicates
that
the
PCnet-32 controller utilizes AMD
79C900 (ILACC) software struc-
tures. In particular, Initialization
Block and Transmit and Receive
descriptor bit maps are affected.
When cleared, this bit indicates
that the PCnet-32 controller util-
izes AMD PCnet-ISA software
structures.
Note: Regardless of
the setting of SSIZE32, the In-
itialization Block must always be-
gin on a double-word boundary.
The value of SSIZE32 is deter-
mined by the PCnet-32 control-
ler. SSIZE32 is read only by the
host.
The PCnet-32 controller uses the
setting of the Software Style reg-
ister (BCR20, bits 7-0) to deter-
mine the value for this bit.
SSIZE32 is cleared by H_RESET
or S_RESET and is not affected
by STOP.
If SSIZE32 is reset, then bits
IADR[31:24] of CSR2 will be
used to generate values for the
upper 8 bits of the 32 bit address
bus during master accesses initi-
ated by the PCnet-32 controller.
This action is required, since the
16-bit software structures speci-
fied by the SSIZE32=0 setting
will yield only 24 bits of address
for PCnet-32 controller bus mas-
ter accesses.
If SSIZE32 is set, then the soft-
ware structures that are common
to the PCnet-32 controller and
the host system will supply a full
32 bits for each address pointer
that is needed by the PCnet-32
controller for performing master
accesses.
The value of the SSIZE32 bit has
no effect on the drive of the upper
8 address pins. The upper 8 ad-
dress pins are always driven, re-
gardless of the state of the
SSIZE32 bit.
Note that the setting of the
SSIZE32 bit has no effect on the
defined width for I/O resources.
I/O resource width is determined
by the state of the DWIO bit.
7-0
SWSTYLE
Software
Style
register.
The
value in this register determines
the “style” of I/O and memory re-
sources that are used by the
PCnet-32 controller. The S/W re-
source style selection will affect
the interpretation of a few bits
within the CSR space and the
width of the descriptors and in-
itialization block. See Table 43.
All PCnet-32 controller CSR bits
and BCR bits and all descriptor,
buffer and initialization block en-
tries not cited in the table above
are unaffected by the Software
Style selection and are therefore
always fully functional as speci-
fied in the BCR and CSR sec-
tions.
Read/write accessible only when
STOP bit is set.
The SWSTYLE register will con-
tain the value 00h following
H_RESET or S_RESET and will
be unaffected by STOP.
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