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參數(shù)資料
| 型號： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 124/220頁 |
| 文件大小： | 1197K |
| 代理商： | AM79C965KCW |
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P R E L I M I N A R Y
AMD
21
Am79C965
Table 8. Data Transfer Sequence from 32-Bit Wide to 16-Bit Wide
BE3
BE2
BE1
BE0
BE3
BE2
BE1
BE0
1
110
NR
1
100
NR
1
000
1
0
1
0
000
0
1
101
NR
1
001
1
0
1
0
001
0
1
011
NR
0
011
NR
0
111
NR
Next with LBS16
Current Access
NR = No second access Required for these cases
During accesses in which PCnet-32 controller is acting
as the VL-Bus target device, the
LBS16 signal will not be
driven. In this case, it is expected that the VL-Bus
required pull-up device will bring the
LBS16 signal to an
inactive level and the PCnet-32 controller will be seen by
the VL-Bus master as a 32-bit peripheral.
LCLK
Local Clock
Input
LCLK is a 1x clock that follows the same phase as a
486-type CPU clock. LCLK is always driven by the sys-
tem logic or the VL-Bus controller to all VL-Bus masters
and targets. The rising edge of the clock signifies the
change of CPU states, and hence, the change of
PCnet-32 controller states.
LDEV
Local Device
Output
LDEV is driven by the PCnet-32 controller when it recog-
nizes an access to PCnet-32 controller I/O space. Such
recognition is dependent upon a valid sampled
ADS
strobe plus valid M/
IO, D/C and ADR31–ADR5 values.
LEADS
Local External Address Strobe
Output
During VL-Bus master write and read accesses the
LEADS pin will be asserted on every T1 cycle as is
specified in the VESA VL-Bus specification, regardless
of the settings of the GCIC bit of BCR18 and the CLL bits
of BCR18.
LGNT
Local Bus Grant
Input
When
LGNT is asserted and LREQ is being asserted by
the PCnet-32 controller, the PCnet-32 controller as-
sumes ownership of the VL bus.
Note that this pin changes polarity when Local Bus
mode has been selected (see pin description of HLDA in
486 Local Bus Interface section).
LGNTO
Local Grant Out
Output
This signal is multiplexed with the TCK pin, and is avail-
able only when the Multi-Interrupt mode has been se-
lected with the JTAGSEL pin.
An additional local bus master may daisy-chain its
LGNT signal through the PCnet-32 controller LGNTO
pin. The PCnet-32 controller will deliver a
LGNTO signal
to the additional local bus master whenever the
PCnet-32 controller receives a
LGNT from the arbitra-
tion logic, but is not simultaneously requesting the bus
internally. The second local bus master must connect its
LREQ output to the LREQI input of the PCnet-32 con-
troller in order to complete the local bus daisy-chain
arbitration control.
When
SLEEP is not asserted, daisy chain arbitration
signals that pass through the PCnet-32 controller will
experience a one-clock delay from input to output (i.e.
LREQI to LREQ and LGNT to LGNTO).
While
SLEEP is asserted (either in snooze mode or
coma mode), if the PCnet-32 controller is configured for
a daisy chain (
LREQI and LGNTO signals have been
selected with the JTAGSEL pin), then the system arbi-
tration signal
LGNT will be passed directly to the daisy-
chain signal
LGNTO without experiencing a one-clock
delay. However, some combinatorial delay will be intro-
duced in this path.
Note that this pin changes polarity when Local Bus
mode has been selected (see pin description of HLDAO
in 486 Local Bus Interface section).
LRDY
Local Ready
Output
LRDY functions as an output from the PCnet-32 control-
ler during PCnet-32 controller slave cycles. During
PCnet-32 controller slave read cycles,
LRDY is as-
serted to indicate that valid data has been presented on
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