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參數(shù)資料
| 型號(hào)： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 175/220頁(yè) |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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AMD
P R E L I M I N A R Y
58
Am79C965
Descriptor DMA Transfers
PCnet-32 controller will determine when a descriptor ac-
cess is required. A descriptor DMA
read will consist of
two doubleword transfers. A descriptor DMA write will
consist of
one or two double word transfer. The trans-
fers within a descriptor DMA transfer mastership period
will always be of the same type (either all read or all
write). The transfers will be to addresses in the order as
specified in Table 19 and Table 20 (note that
MD indi-
cates
TMD or RMD).
If buffer chaining is used (see Transmit and Receive De-
scriptor Table Entry sections),
writes to the descriptors
that do not contain the End of Packet bit will consist of
only one doubleword. This write will be to the same loca-
tion as the second of the two writes performed when the
End of Frame has been processed (i.e. to the location
that contains the descriptor OWNership bit, MD1[31]).
Descriptor DMA transfers will never be executed using
linear burst mode. During read accesses, the byte en-
able signals will indicate that all byte lanes are active.
Should some of the bytes not be needed, then the
PCnet-32 controller will internally discard the extrane-
ous information that was gathered during such a read.
During write accesses, only the bytes which
need to be
written are enabled, by activating the corresponding
byte enable pins. See Figure 9 and Figure 10.
If a
bus preemption event occurs during a descriptor
DMA transfer, then the PCnet-32 controller will com-
plete both of the two data transfer cycles of the descrip-
tor DMA transfer, before releasing the HOLD signal and
relinquishing the bus.
The only significant differences between descriptor
DMA transfers and initialization DMA transfers are that
the addresses of the accesses follow different ordering.
Table 19. Bus Master Reads of Descriptors
Address
LANCE
PCnet-32
Address
LANCE
PCnet-32
Sequence A[7:0]
Item Accessed
Sequence A[7:0]*
Item Accessed
00
MD1[15:0],
MD1[31:24],
04
MD1[15:8],
MD1[31:0]
MD0[15:0]
MD0[23:0]
MD2[15:0]
04
MD3[15:0],
MD2[15:0],
00
MD1[7:0],
MD0[31:0]
MD2[15:0]
MD1[15:0]
MD0[15:0]
Bus Break
32-Bit Software Mode
16-Bit Software Mode
Table 20. Bus Master Writes of Descriptors
Address
LANCE
PCnet-32
Address
LANCE
PCnet-32
Sequence A[7:0]
Item Accessed
Sequence A[7:0]*
Item Accessed
04
MD3[15:0],
MD2[15:0],
08
MD3[15:0],
MD2[31:0]
MD2[15:0]
MD1[15:0]
MD2[15:0]
00
MD1[15:0],
MD1[31:24],
04
MD1[15:8],
MD1[31:0]
MD0[15:0]
MD0[23:0]
MD2[15:0]
Bus Break
32-Bit Software Mode
16-Bit Software Mode
*Address values for A[31:8] are constant throughout any single descriptor DMA transfer. Note that even though bits A[1:0] do not
physically exist in the system, these bits must be set to ZERO in the descriptor base address.
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