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參數(shù)資料
| 型號(hào)： | AM79C965KCW |
| 廠(chǎng)商： | ADVANCED MICRO DEVICES INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁(yè)數(shù)： | 11/220頁(yè) |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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AMD
P R E L I M I N A R Y
108
Am79C965
that the upper 16 bits of all BCR locations are reserved
and written as zeros and read as undefined. Therefore,
during BDP write operations in DWIO mode, the upper
16 bits of all BCR locations should be written as zeros.
Reset Register (S_RESET)
A read of the reset register creates an internal
S_RESET pulse in the PCnet-32 controller. This read
access cycle must be 16 bits wide in WIO mode and 32
bits wide in DWIO mode. The internal S_RESET pulse
that is generated by this access is different from both the
assertion of the hardware RESET pin (H_RESET) and
from the assertion of the software STOP bit. Specifi-
cally, the Reset register’s S_RESET will be the equiva-
lent of the assertion of the RESET pin (H_RESET)
assertion for all CSR locations, but S_RESET will have
no effect at all on the BCR locations, and S_RESET will
not cause a deassertion of the HOLD pin.
The NE2100 LANCE based family of Ethernet cards re-
quires that a write access to the reset register follows
each read access to the reset register. The PCnet-32
controller does not have a similar requirement. The write
access is not required but it does not have any harmful
effects.
Write accesses to the reset register will have no effect
on the PCnet-32 controller.
Note that a read of the Reset register will take longer
than the normal I/O access time of the PCnet-32 control-
ler. This is because an internal S_RESET pulse will be
generated due to this access, and the access will not be
allowed to complete on the system bus until the internal
S_RESET operation has been completed. This is to
avoid the problem of allowing a new I/O access to pro-
ceed while the S_RESET operation has not yet com-
pleted, which would result in erroneous data being
returned by (or written into) the PCnet-32 controller. The
length of a read of the Reset register can be as long as
128 BCLK cycles when Am386 mode has been selected
and 64 BCLK cycles when Am486 mode or VESA VL-
Bus mode has been selected.
Note that a read of the Reset register will not cause a
deassertion of the HOLD signal, if it happens to be ac-
tive at the time of the read to the reset register. The
HOLD signal will remain active until the HLDA signal is
synchronously sampled as asserted. Following the read
of the RESET register, on the next clock cycle after the
HLDA signal is synchronously sampled as asserted, the
PCnet-32 controller will deassert the HOLD signal). No
bus master accesses will have been performed during
this brief bus ownership period.
Note that this behavior differs from that which occurs fol-
lowing the assertion of a minimum-width pulse on the
RESET pin (H_RESET). A RESET pin assertion will
cause the HOLD signal to deassert within six clock cy-
cles following the assertion. In the RESET pin case, the
PCnet-32 controller will not wait for the assertion of the
HLDA signal before deasserting the HOLD signal.
Vendor Specific Word
This I/O offset is reserved for use by the system de-
signer. The PCnet-32 controller will not respond to ac-
cesses directed toward this offset.
Reserved I/O Space
These locations are reserved for future use by AMD.
The PCnet-32 controller does not respond to accesses
directed toward these locations, but future AMD prod-
ucts that are intended to be upward compatible with the
PCnet-32 controller may decode accesses to these lo-
cations. Therefore, the system designer may not utilize
these I/O locations.
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PDF描述 |
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| AJ80A-024L-033F50 | 1-OUTPUT 240 W DC-DC REG PWR SUPPLY MODULE |
| AM93LC66S | 4096-bits Serial Electrically Erasable PROM |
| AM93LC66SA | 4096-bits Serial Electrically Erasable PROM |
| AM93LC66VN | 4096-bits Serial Electrically Erasable PROM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C970 | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnetTM-PCI Single-Chip Ethernet Controller for PCI Local Bus |
| AM79C970A | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC | 制造商:AMD 制造商全稱(chēng):Advanced Micro Devices 功能描述:PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product |
| AM79C970AKC\\W | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Advanced Micro Devices 功能描述: |
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