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參數(shù)資料
| 型號(hào)： | AM79C965KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 3 CHANNEL(S), LOCAL AREA NETWORK CONTROLLER, PQFP16 |
| 封裝： | PLASTIC, QFP-160 |
| 文件頁數(shù)： | 181/220頁 |
| 文件大?。?/td> | 1197K |
| 代理商： | AM79C965KCW |
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P R E L I M I N A R Y
AMD
63
Am79C965
Transfers within a linear burst cycle will either be all read
or all write cycles, and will always be to contiguous as-
cending addresses. Linear Bursting of Read and Write
operations can be individually enabled or disabled
through the BREADE and BWRITE bits of BCR18 (bits 6
and 5).
Linear Burst DMA transfers should be considered as a
superset of the FIFO DMA transfers. Linear burst DMA
transfers will only be used for data transfers to and from
the PCnet-32 controller FIFOs and they will only be al-
lowed when the burst enable bits of BCR18 have been
set. Linear Read bursting and Linear Write bursting
have individual enable bits in BCR18. Any combination
of linear burst enable bit settings is permissible.
Linear bursting is not allowed in systems that have
BCLK frequencies above 33 MHz. Linear bursting is
automatically disabled in VL-Bus systems that operate
above this frequency by connecting the VLBEN pin to
either ID(3) (for VL-Bus version 1.0 systems) or ID(4)
AND ID(3) AND ID(1) AND
ID(0) (for VL-Bus version 1.1
or 2.0 systems). In Am486-style systems that have
BCLK frequencies above 33 MHz, disabling the linear
burst capability is ideally carried out through EEPROM
bit programming, since the EEPROM programming can
be setup for a particular machine’s architecture.
All byte lanes are always considered to be active during
all linear burst transfers. The
BE3–BE0 signals will re-
flect this fact.
Linear Burst DMA Starting Address Restrictions
A PCnet-32 controller linear burst will begin only when
the address of the current transfer meets the following
condition:
A[31:0] MOD (LINBC x 16) = 0,
The following table illustrates all possible starting ad-
dress values for all legal LINBC values. Note that
A[31:6] are don’t care values for all addresses. Also note
that while A[1:0] do not physically exist within a 32 bit
system, they are valid bits within the buffer pointer field
of descriptor word 0. Thus, where A[1:0] are listed, they
refer to the lowest two bits of the descriptor’s buffer
pointer field. These bits will have an affect on determin-
ing when a PCnet-32 controller linear burst operation
may legally begin and they will affect the output values
of the
BE3–BE0 pins, therefore they have been included
in Table 21 as A[1:0].
It is not necessary for the software to insure that the
buffer address pointer contained in descriptor word 0
matches the address restrictions given in the table.
If the
buffer pointer does not meet the conditions set forth in
the table, then the PCnet-32 controller will simply post-
pone the start of linear bursting until enough ordinary
FIFO DMA transfers have been performed to bring the
current working buffer pointer value to a valid linear
burst starting address. This operation is referred to as
“aligning” the buffer address to a valid linear burst start-
ing address. Once this has been done, the PCnet-32
controller will recognize that the address for the current
access is a valid linear burst starting address, and it will
automatically begin to perform linear burst accesses at
that time, provided of course that the software has en-
abled the linear burst mode.
Note that if the software
would provide only valid linear
burst starting addresses in the buffer pointer, then the
PCnet-32 controller could avoid performing the align-
ment operation. It would begin linear burst accesses on
the very first of the buffer transfers thereby allowing a
slight gain in bus bandwidth efficiency.
Because of the linear burst starting address restrictions
given in the table above, the PCnet-32 controller linear
burst
mode
is
completely
compatible
with
the
Am486-style burst cycle when the LINBC[2:0] bits have
been programmed with the value of 001.
Table 21. Linear Burst Addresses
Linear Burst Addresses
LBS = Linear Burst
Beginning A[5:0] =
LINBC[2:0]
Size (No. of Transfers)
(A[31:6] = Don’t Care)
0
0 (no linear bursting)
Not Applicable
1
4
00, 10, 20, 30
2
8
00, 20
416
00
3,5,6,7
Reserved
Not Applicable
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