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型號(hào)：	XPC801ZP25
元件分類：	微處理器
英文描述：	Microprocessor
中文描述：	微處理器
文件頁(yè)數(shù)：	102/605頁(yè)
文件大小：	2380K
代理商：	XPC801ZP25

The PowerPC Core

MPC801 USER’S MANUAL

6.2.5 Processing An Interrupt

The following table shows the significant events that occur when an interrupt is processed.

Table 6-3. Special Ports to the Machine State Register Bits

External Interrupt Enable:

End of Interrupt Handler’s Prologue, Enable Nested

External Interrupts;

End of Critical Code Segment in Which External Interrupts

Were Disabled

External Interrupt Disable, But Other Interrupts Are Recoverable:

End of Interrupt Handler’s Prologue, Keep External

Nested Interrupts Disabled;

Start of Critical Code Segment in Which External

Interrupts Are Disabled

Nonrecoverable Interrupt:

Start of Interrupt Handler’s Epilogue

Table 6-4. Interrupt Latency

INSTRUCTION COMPLETE

KILL PIPELINE

Faulting Instruction

Instruction Complete

and All Previous

Instructions Complete

Kill Pipeline

B + 3 Clocks

First Instruction of

Handler Issued

At time point A an instruction is issued that is destined to cause an interrupt.

At time point B the excepting instruction has reached the head of the history queue, thus implying that all instructions

preceding it in the code stream have finished execution without generating an interrupt. Also, the excepting instruction itself

has completed execution. At this time the exception is “recognized” and exception processing begins. If, at this point, the

instruction had not generated an exception, it would have been retired.

At time point C the sequencer starts to fetch the interrupt handler’s first instruction.

By time point D the state of the machine prior to the issue of the excepting instruction is restored (the machine is restored to

its state at the time.

At time point E the MSR and instruction pointer of the executing process have been saved and control has been transferred

to the interrupt handler routine.

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