Clocks and Power Control
MOTOROLA
MPC801 USER’S MANUAL
5-13
5
XFC—External Filter Capacitor
This pin connects to the off-chip capacitor for the PLL filter. One terminal of the capacitor is
connected to XFC and the other is connected to VDDSYN.
NOTE
30M
is the minimum parasitic resistance value that ensures
proper PLL operation when connected in parallel
with the XFC capacitor.
5.7 CONTROLLING THE SYSTEM CLOCK
The system phase-loop lock has a 32-bit control register that is powered by keep alive
power. This system clock and reset control register (SCCR) is memory-mapped into the
MPC801 system interface unit register map.
Bits 0, 3–5, and 9—Reserved
These bits are reserved and should be set to 0.
COM—Clock Output Mode
These bits control the output buffer strength of the CLKOUT pin. When both bits are set, the
CLKOUT pin is held in the high (1) state. These bits can be dynamically changed without
generating spikes on the CLKOUT pin. If the CLKOUT pin is not connected to external
circuits, both bits (disabling CLKOUT) should be set to minimize noise and power
dissipation. The COM bits are cleared by a hard reset.
00 = Clock output enabled full-strength output buffer.
01 = Clock output enabled half-strength output buffer.
10 = Reserved.
11 = Clock output disabled.
Table 5-4. XFC Capacitor Values
MINIMUM CAPACITANCE
MAXIMUM CAPACITANCE
UNIT
MF < = 4
XFC = MF * 425 - 125
XFC = MF * 590 - 175
pF
MF > 4
XFC = MF * 520
XFC = MF * 920
pF
SCCR
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIELD
RES
COM
RESERVED
TBS
RTDIV
RTSEL
RES
PRQEN
RESERVED
EBDF
RES
BIT
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FIELD
RES
DFSYNC
DFBRG
DFNL
DFNH
RESERVED