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參數(shù)資料
| 型號： | XPC801ZP25 |
| 元件分類： | 微處理器 |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 600/605頁 |
| 文件大小： | 2380K |
| 代理商： | XPC801ZP25 |
Index
MOTOROLA
MPC801 USER’S MANUAL
Index-9
INDEX
PowerPC standards
PowerPC Operating Environment Architecture
(Book 3), 7-6
branch processor registers,
7-6
fixed-point processor
special purpose registers,
7-6
interrupts,
7-8
optional facilities and instructions,
7-17
reference and change bits,
7-7
storage control instructions,
7-7
storage model,
7-7
storage protection,
7-7
timer facilities,
7-17
PowerPC User Instruction Set Architecture
(Book 1), 7-1
branch instructions,
7-2
branch processor,
7-2
computation modes,
7-1
exceptions,
7-2
fixed point-processor,
7-2
instruction classes,
7-1
instruction fetching,
7-2
load/store processor,
7-3
reserved fields,
7-1
PowerPC Virtual Environment Architecture
(Book 2), 7-4
operand placement effects,
7-4
storage control instructions,
7-5
storage model,
7-4
timebase,
7-6
PowerQUICC, porting to,
B-43
prescaler,
16-8
program flow tracking, 18-1
external hardware,
18-5
features,
18-1
instruction fetch show cycle control,
18-8
internal hardware,
18-2
program interrupt,
7-11
program trace cycle,
18-2
program trace in debug mode,
18-5
program trace, reconstructing,
18-2
programmable phase-locked loop,
5-1
programming models
I
2
C,
16-30
serial controller,
16-15
serial peripheral interface,
16-20
protection of development port registers,
18-41
protection,
12-2
PS,
12-12
PTE,
12-12
PTR,
2-7
,
13-5
,
13-33
Q
queue flush information special case,
18-4
QUICC,
1-1
QUICC/PowerQUICC differences
bit labeling,
B-44
cache,
B-44
configuration, B-27
DRAM,
B-34
EPROM,
B-31
SRAM,
B-27
initialization,
B-1
MMU/cache example,
B-5
porting to the PowerQUICC,
B-43
programming the UPM,
B-2
R
RAM array size,
15-23
RAM word structure and timing
specifications,
15-25
RD/WR,
2-2
,
13-4
read cycle, data bus requirements,
13-26
read hit,
10-7
read miss,
10-7
read/write (RD/WR),
13-32
reading the data cache,
10-7
,
10-11
real-time clock (RTC), 12-3
,
12-11
block diagram,
12-12
real-time clock alarm register,
12-27
real-time clock register,
12-27
real-time clock status and control register,
12-26
receiver register,
16-6
receiver,
16-5
recoverable interrupt bit (MSRRI),
6-10
register unit, 6-15
control registers, 6-15
initialization, 6-24
hard/soft reset,
6-24
system reset interrupt,
6-24
registers
BAR,
6-31
base,
15-6
,
15-70
,
B-28
baud control,
16-11
boundary scan,
19-4
branch processor, 7-6
machine state register,
7-6
processor version register,
7-6
breakpoint address,
6-31
core control,
A-1
DAR,
6-31
data cache special,
10-3
debug mode,
18-51
decrementer,
12-23
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