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Applications
MOTOROLA
MPC801 USER’S MANUAL
B-27
B
For each system clock a separate 32-bit word defines the behavior of the address
multiplexing, address incrementing, and control signal assertion and negation to a quarter
of a system clock resolution. It also defines the transfer acknowledge assertion. Different
behavior can be defined for different types of access (read, write, burst read, and burst
write).
B.2.1 General Configuration
After power-up, certain registers need initialization, assuming that initial system
configuration is complete. The features of each memory bank are programmed through
three registers—option register (OR), base register (BR), and machine mode register
(MMR). There is an individual OR and BR for each of the eight memory banks.
B.2.2 SRAM Configuration
This application uses a 512K SRAM bank arranged in a 32-bit port. It is implemented using
four Motorola MC6226A 128K
×
8 CMOS fast-static RAMs. These are available with access
times of 20 to 45ns. The 45ns are sufficient devices that interact with the MPC801 using the
2-clock fast termination cycle. The CS3* signal is used to select the SRAM memory bank.
Individual byte strobes are provide via the WE*[3:0] signals. The OE* signal is used to
control the output enable of the SRAM.
Figure B-1. General System Configuration
To select the memory bank as an SRAM bank, the MS[0:1] bits in the base register should
be set at 00. This selects the memory bank to be controlled by the GPCM. When the bank
is selected as a GPCM bank, the BI bit in the option register should be set.
DATA(31:0)
ADDR(11:2)
CAS(3:0)
RAS
R/W
DRAM
DATA(31:0)
ADDR(18:2)
SRAM
G
EN
DATA(31:24)
ADDR(19:0)
EPROM
G
EN
D31-0
D31-0
D31-24
A11:2
CAS3:0
CS1
R/W
A18:2
A19:0
CS3
CS0
WE3:0
OE
MPC860
MPC801
System Bus
1Mx32
512K x32
128K x 8
MCM54400A
MCM6226A
27C010