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MPC801
USER’S MANUAL
MOTOROLA
LIST OF ILLUSTRATIONS
Figure
Number
Page
Number
Title
1-1.
1-2.
MPC801 Block Diagram ........................................................................1-4
MPC801 System Configuration .............................................................1-8
2-1.
MPC801 External Signals .....................................................................2-1
4-1.
4-2.
Reset Configuration Basic Scheme .......................................................4-6
Reset Configuration Sampling Scheme For Short PORESET
Assertion ...............................................................................................4-7
Reset Configuration Sampling Scheme For Long PORESET
Assertion ...............................................................................................4-7
Reset Configuration Sampling Timing Requirements ...........................4-8
4-3.
4-4.
5-1.
5-2.
5-3.
5-4.
5-5.
5-6.
5-7.
5-8.
5-9.
5-10.
5-11.
Clock Unit Block Diagram ......................................................................5-2
MPC801 Power Supply .........................................................................5-3
MPC801 Clocks Timing Diagram ..........................................................5-4
System PLL Block Diagram ...................................................................5-7
General System Clocks Select ..............................................................5-9
Divided System Clocks Timing Diagram .............................................5-10
MPC801 Clocks For DFNH = 1 or DFNL = 0 Timing Diagram ............5-11
MPC801 Low-Power Modes Flowchart ...............................................5-19
MPC801 Basic Power Supply Configuration .......................................5-22
External Power Supply Scheme (2.0 V Internal Voltage) ....................5-23
Key Mechanism Diagram ....................................................................5-24
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
Core Block Diagram ..............................................................................6-3
Instruction Flow Conceptual Diagram ...................................................6-3
Basic Instruction Pipeline Timing Diagram ............................................6-4
Sequencer Data Path ............................................................................6-5
History Buffer Queue .............................................................................6-9
Load/Store Unit Functional Block Diagram .........................................6-26
Number of Bus Cycles Needed For Unaligned, Single Register
Fixed-Point Load/Store Instructions ....................................................6-28
Number of Bus Cycles Needed For String Instruction Execution .......6-30
6-8.