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The PowerPC Core
6-14
MPC801 USER’S MANUAL
MOTOROLA
6
More than one asynchronous interrupt cause can be present at any time. However, when
more than one interrupt causes are present, only the highest priority interrupt is taken, as
shown in the following table.
Table 6-5. Detection Order of Instruction-Related Interrupts
NUMBER
INTERRUPT TYPE
CAUSED BY
1
Trace
Trace Bit Asserted
1
2
Implementation Dependent Instruction TLB Miss
Instruction MMU TLB Miss
3
Implementation Dependent Instruction TLB Error
Instruction MMU Protection / Translation Error
4
Machine Check Interrupt
Fetch Error
5
Debug I- Breakpoint
Match Detection
6
Implementation Dependent Software Emulation Interrupt
Attempt to Invoke Unimplemented Feature
1
Floating Point Unavailable
Attempt to is Made to Execute Floating Point Instruction
and MSR
FP
=0
7
2
Privileged Instruction
Attempt to Execute Privileged Instruction in Problem Mode
Alignment Interrupt
Load/Store Checking
System Call Interrupt
SC Instruction
Trap
Trap Instruction
8
Implementation Dependent Data TLB Miss
Data MMU TLB Miss
9
Implementation Dependent Data TLB Error
Data MMU TLB Protection / Translation Error
10
Machine Check Interrupt
Load or Store Access Error
11
Debug L- Breakpoint
Match Detection
NOTES: 1.
The trace mechanism is implemented by letting one instruction go as if no trace is enabled and trapping the second
instruction. This, of course, refers to this second instruction.
2.
Exclusive for any one instruction.
Table 6-6. Interrupt Priorities Mapping
NUMBER
INTERRUPT TYPE
CAUSED BY
1
Development Port Nonmaskable Interrupt
Signal From the Development Port
2
System Reset
NMI_L Assertion
3
Instruction-related Interrupts
Instruction Processing
4
Peripheral Breakpoint Request or Development Port Maskable Interrupt
Breakpoint Signal From Any Peripheral
5
External Interrupt
Signal From the Interrupt Controller
6
Decrementer Interrupt
Decrementer Request