Applications
B-28
MPC801 USER’S MANUAL
MOTOROLA
B
Defining the memory map of the SRAM bank is achieved by setting several options. The
SRAM port size can be defined as 32-bit by setting the PS[0:1] bits in the base register to
00. The base location of the memory bank is selected by setting the BA[0:16] bits in the base
register. This allows the block to be defined on 32K boundaries. For example, if a base
location of 20000000H is required, these bits would be set as 0010 0000 0000 0000 0B.
The size of the SRAM bank is defined by the address mask bits (AM[0:16]) in the option
register. This enables blocks sizes between 32K and 4G to be selected. For example, if a
block size of 1M, 80000H, these bits should be set to 0000 0000 0000 1111 1B. PARE in
the base register is used to enable parity checking. Since parity it is not required in this
design, this bit is cleared. Other functions, such as write protect (WP), and address type
operation (AT[0:2]/ATM[0:2]) can be defined as needed.
Table B-9. Option Register
BIT 0
AM0
BIT 1
AM1
BIT 2
AM2
BIT 3
AM3
BIT 4
AM4
BIT 5
AM5
BIT 6
AM6
BIT 7
AM7
BIT 8
AM8
BIT 9
AM9
BIT 10
AM10
BIT 11
AM11
BIT 12
AM12
BIT 13
AM13
BIT 14
AM14
BIT 15
AM15
BIT 16
AM16
BIT 17
ATM0
BIT 18
ATM1
BIT 19
ATM2
BIT 20
CSNT/SAM
BIT 21
ACS0
BIT 22
ACS1
BIT 23
BI
BIT 24
SCY0
BIT 25
SCY1
BIT 26
SCY2
BIT 27
SCY3
BIT 28
SETA
BIT 29
TRLX
BIT 30
RES
BIT 31
RES
Table B-10. Base Register
BIT 0
BA0
BIT 1
BA1
BIT 2
BA2
BIT 3
BA3
BIT 4
BA4
BIT 5
BA5
BIT 6
BA6
BIT 7
BA7
BIT 8
BA8
BIT 9
BA9
BIT 10
BA10
BIT 11
BA11
BIT 12
BA12
BIT 13
BA13
BIT 14
BA14
BIT 15
BA15
BIT 16
BA16
BIT 17
AT0
BIT 18
AT1
BIT 19
AT2
BIT 20
PS0
BIT 21
PS1
BIT 22
PARE
BIT 23
WP
BIT 24
MS0
BIT 25
MS1
BIT 26
RES
BIT 27
RES
BIT 28
RES
BIT 29
RES
BIT 30
RES
BIT 31
V