777米奇影院狠狠狠,国产精品三级在线观看

您好，
買賣IC網(wǎng)歡迎您。
請(qǐng)登錄
免費(fèi)注冊(cè)

您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372925 > XPC801ZP25 Microprocessor PDF資料下載

型號(hào)：	XPC801ZP25
元件分類：	微處理器
英文描述：	Microprocessor
中文描述：	微處理器
文件頁(yè)數(shù)：	571/605頁(yè)
文件大?。?/td>	2380K
代理商：	XPC801ZP25

Applications

MPC801 USER’S MANUAL

For the RPN bits with 8M pages, the value changes every 1K entry:

For L1D40 and L1D41, RPN = $10000.

For L1D42 and L1D43, RPN = $10800.

For L1D44 and L1D45, RPN = $11000.

For L1D46 and L1D47, RPN = $11800.

For L1D48 and L1D49, RPN = $12000.

For L1D4A and L1D4B, RPN = $12800.

For L1D4C and L1D4D, RPN = $13000.

For L1D4E and L1D4F, RPN = $13800.

For L1D50 and L1D51, RPN = $14000.

For L1D52 and L1D53, RPN = $14800.

For L1D54 and L1D55, RPN = $15000.

For L1D56 and L1D57, RPN = $15800.

For L1D58 and L1D59, RPN = $16000.

For L1D5A and L1D5B, RPN = $16800.

For L1D5C and L1D5D, RPN = $17000.

For L1D5E and L1D5F, RPN = $17800.

B.2 CONFIGURING THE MPC801 MEMORY CONTROLLER

A fundamental design goal of the PowerQUICC was to have an easy interface to other

system components. To achieve this goal, the system interface unit incorporates a flexible

memory controller. Each of the eight memory banks can be configured to support various

memory types (Flash EPROM, SRAM, DRAM, EDO DRAM, or synchronous DRAM). The

assertion and negation of the memory control signals (CS, WE, OE, BS, and

general-purpose lines) are defined by the software up to a quarter of a system clock

resolution, so it is likely the MPC801 can interface to any type of memory. The PowerQUICC

facilitates the different types of memory by means of the three machines included in the

memory controller:

The general-purpose chip-select machine (GPCM)

The user-programmable machine A (UPMA)

The user-programmable machine B (UPMB)

Each of the eight chip-selects can be controlled by any of the three machines. The GPCM

handles standard accesses to SRAM, EPROM, FEPROM, and simple peripherals. Port

sizes of 8-, 16-, and 32-bit are supported with individual byte write enable (WE) and output

enable (OE) control. Therefore, all simple memory interfaces are supported gluelessly with

The user-rogrammable machines (UPMs) offer great flexibility in the definition of memory

cycles. Each UPM can control the address multiplexing required for DRAM devices, the

timing of four byte enables (BE0:3), and the timing of six general-purpose lines (GPL0:5).

The UPM is completely controlled by the software and it runs a specific pattern for a

programmable number of clock cycles.

相關(guān)PDF資料	PDF描述
XPC801ZP40	Microprocessor
XPC821ZP40	Microprocessor
XPC823ZP25	Microprocessor
XPC823ZP50	Microprocessor
XPC8241LZP166	Microprocessor

相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
XPC801ZP40	制造商:未知廠家制造商全稱:未知廠家功能描述:Microprocessor
XPC821ZP40	制造商:未知廠家制造商全稱:未知廠家功能描述:Microprocessor
XPC823CVR66B2T	功能描述:IC MPU POWERQUICC 66MHZ 256-PBGA RoHS:是類別:集成電路 (IC) >> 嵌入式 - 微處理器系列:MPC8xx 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA（25x25）包裝:托盤
XPC823CZC66A	制造商:Freescale Semiconductor 功能描述:
XPC823CZT66B2	制造商:Freescale Semiconductor 功能描述:

發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

(若只采購(gòu)一條型號(hào)，填寫一行即可)

*型號(hào)	*數(shù)量	廠商	批號(hào)	封裝

采購(gòu)需求

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

我的聯(lián)系方式

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)