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Memory Controller
MOTOROLA
MPC801 USER’S MANUAL
15-25
15
15.2.3.1 RAM WORD STRUCTURE AND TIMING SPECIFICATION
The RAM word structure is illustrated in Figure 15-27 and described in Table 15-2. With
typical DRAM, the CS signals correspond to RAS and the BS signals correspond to CAS.
Likewise, the GPL signals can be used as output enables.
Figure 15-27. RAM Word Structure
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
CST4
CST1
CST2
CST3
BST4
BST1
BST2
BST3
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
BIT 13
BIT 14
BIT 15
G0L0
G0L1
G0H0
G0H1
G1T4
G1T3
G2T4
G2T3
BIT 16
BIT 17
BIT 18
BIT 19
BIT 20
BIT 21
BIT 22
BIT 23
G3T4
G3T3
G4T4/DLT3
G4T3/WAEN
G5T4
G5T3
RESERVED
RESERVED
BIT 24
BIT 25
BIT 26
BIT 27
BIT 28
BIT 29
BIT 30
BIT 31
LOOP
EXEN
AMX0
AMX1
NA
UTA
TODT
LAST
Table 15-2. UPM RAM Word
BITS
MNEMONIC
FUNCTION
0
CST4
CST4 = 0 means the value of the CS signal at the trailing edge of GCLK2 will be ‘0’
CST4 = 1 means the value of the CS signal at the trailing edge of GCLK2 will be ‘1’
1
CST1
CST1 = 0 means the value of the CS signal at the rising edge of GCLK1 will be ‘0’
CST1 = 1 means the value of the CS signal at the rising edge of GCLK1 will be ‘1’
2
CST2
CST2 = 0 means the value of the CS signal at the rising edge of GCLK2 will be ‘0’
CST2 = 1 means the value of the CS signal at the rising edge of GCLK2 will be ‘1’
3
CST3
CST3 = 0 means the value of the CS signal at the trailing edge of GCLK1 will be ‘0’
CST3 = 1 means the value of the CS signal at the trailing edge of GCLK1 will be ‘1’
4
BST4
BST4 = 0 means the value of the BS signals at the trailing edge of GCLK2 will be ‘0’
BST4 = 1 means the value of the BS signals at the trailing edge of GCLK2 will be ‘1’
NOTE:
The final value of the BS signals depends on the value of the PS bits in the BR accessed,
the value of the TSIZ signals for the access, and the value of the A[30:31] signals.
For more information about the BS signals, see
Timing Specification
.
Section 15.2.3.1 RAM Word Structure and