![](http://datasheet.mmic.net.cn/290000/XPC801ZP25_datasheet_16187868/XPC801ZP25_135.png)
PowerPC Architecture Compliance
7-12
MPC801 USER’S MANUAL
MOTOROLA
7
MSR—Machine State Register
IP
No change.
ME
No change.
LE
Bits are copied from the ILE.
Other
Set to 0.
Execution resumes at offset x’00D00’ from the base address indicated by MSR
IP
.
7.3.7.3.9 Floating-Point Assist Interrupt.
The floating-point assist interrupt is not
generated by the MPC801. An implementation dependent software emulation interrupt will
be taken on any attempt to execute a floating-point instruction.
7.3.7.3.10 Implementation Dependent Software Emulation Interrupt.
An
implementation dependent software emulation interrupt occurs as a result of one of the
following conditions:
When executing any unimplemented instruction, including all illegal and
unimplemented optional and floating-point instructions.
When executing a
mtspr
or
mfspr
that specifies an on-core unimplemented register,
regardless of SPR
0
.
When executing a
mtspr
or
mfspr
that specifies an off-core unimplemented register
and SPR
0
=0 or MSR
PR
=0. Refer to
Section 7.3.7.3.6 Program Interrupt
for more
information.
In addition, the following registers are set:
SRR0—Save/Restore Register 0
Set to the effective address of the instruction that caused the interrupt.
SRR1—Save/Restore Register 1
1–4
Set to 0.
10–15
Set to 0.
Other
Loaded from bits 16–31 of the MSR. In the current implementation, Bit 30 of
the SRR1 is never cleared, except by loading a zero value from MSR
RI
.
MSR—Machine State Register
IP
No change.
ME
No change.
LE
Bits are copied from the ILE.
Other
Set to 0.
Execution resumes at offset x’01000’ from the base address indicated by MSR
IP
.