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Index
MOTOROLA
MPC801 USER’S MANUAL
Index-7
INDEX
M
M_TW,
11-15
M_TWB,
11-14
machine A mode register,
15-75
machine B mode register,
15-78
machine check interrupt,
7-9
machine state register (MSR),
6-10
machine state, nonrestartable,
18-9
MAMR,
15-6
,
15-20
MAR,
15-6
,
15-21
masked,
18-9
master
external arbitration phase,
13-27
master mode, 16-17
,
16-18
,
16-26
I
2
C,
16-28
matches on bytes and half-words,
18-12
maximum ratings,
20-1
MBMR,
15-6
,
15-20
MC68360 Quad Integrated Communications
Controller (QUICC),
1-1
MCR,
15-6
,
15-20
MD_AP,
11-13
MD_CTR,
11-12
MD_DCAM,
11-25
MD_DRAM0,
11-26
MD_DRAM1,
11-27
MD_EPN,
11-18
MD_RPN,
11-20
MD_TWC,
11-19
MDR,
15-6
,
15-20
MEMC memory map,
3-2
,
A-6
memory address register,
15-84
memory banks,
15-3
memory coherence,
7-4
memory command register,
15-82
memory controller, 15-1
architecture,
15-3
block diagram,
15-2
external master support,
15-59
features,
15-1
general-purpose chip-select machine,
15-7
programming model,
15-68
registers,
15-6
user-programmable machine, 15-19
memory periodic timer request block
diagram,
15-20
memory data register,
15-84
memory devices,
15-59
memory management unit, 11-1
address translation,
11-2
features,
11-1
interrupts,
11-29
programming model,
11-10
protection,
11-3
requirements for accessing the control
registers,
11-32
storage attributes,
11-4
reference and change bit updates,
11-4
storage control,
11-4
TLB manipulation,
11-30
translation lookaside buffer,
11-2
translation table structure, 11-4
level one descriptor, 11-8
level two descriptor,
11-9
memory map, 3-1
clocks and reset,
3-4
,
A-7
I
2
C,
3-3
,
A-8
MEMC,
3-2
,
A-6
Port B,
3-3
,
A-9
serial controller,
3-3
,
A-8
serial peripheral interface,
3-3
,
A-8
system integration timers,
3-4
,
A-7
system interface unit,
3-1
,
A-5
UART,
3-1
,
A-5
memory periodic timer prescaler register,
15-69
messages, receiving,
16-29
mfspr,
18-41
MI_AP,
11-11
MI_CTR,
11-10
MI_DCAM,
11-22
MI_DRAM0,
11-23
MI_DRAM1,
11-24
MI_EPN,
11-15
MI_RPN,
11-17
MI_TWC,
11-16
MMU tablewalk base register,
11-14
MMU tablewalk scratch register,
11-15
MMU,
11-1
MODCK1 and MODCK2,
2-7
modes, 18-20
copyback,
10-8
I
2
C,
16-28
low power,
5-18
writethrough,
10-9
Motorola BSDL description,
19-19
MPC801
applications, 1-7
,
B-1
architecture overview,
1-4
features,
1-1
system configuration,
1-8
MPC801 PowerPC Quad Integrated
Communications Controller (PowerQUICC),
1-1
MSR bit special ports,
6-11
MSR,
7-9
,
7-16
MSREE bit,
6-11
MSRRI bit,
6-11
MSTAT,
15-6
mtspr,
18-41
multi-master operation,
16-19