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Memory Controller
15-6
MPC801 USER’S MANUAL
MOTOROLA
15
Figure 15-4. Memory Controller Basic Operation
15.2.1 Registers Associated with the Memory Controller
The status bits for each one of the memory banks are in the memory controller status
(MSTAT) register and there is only one MSTAT for the entire memory controller. Each
memory bank has a base register (BR) and an option register (OR). The MSTAT register
reports write-protect violations that occur and parity errors for every bank. The BR
registers are specific memory to bank
x
. The BR contains a V bit that indicates when there
is valid register information for that chip-select.
x
and OR
x
Each of the option registers define the attributes for the general-purpose chip-select
machine when the corresponding bank is accessed. The option registers also define the
initial address multiplexing for a memory cycle controlled by a user-programmable machine.
The machine A mode register (MAMR) and machine B mode register (MBMR) define most
of the global features for the user-programmable machines.
The memory command register (MCR) and memory data register (MDR) are used to
initialize the user-programmable machine’s RAM and to specify which pattern the software
must run. The memory address register (MAR) allows a specific pattern to output this
register’s data to the address pins.
EXTERNAL SIGNALS
TIMING GENERATOR
EXTERNAL MEMORY ACCESS REQUEST
PROGRAMMABLE
MACHINE A
GENERAL-PURPOSE
CHIP-SELECT
MACHINE
EXTERNAL SIGNALS
TIMING GENERATOR
MS
ADDRESS COMPARATOR
BANK SELECT
MUX
EXTERNAL SIGNALS
ADDRESS, ADDRESS TYPE
BURST, RD/WR
USER-
PROGRAMMABLE
MACHINE B
USER-