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Electrical Characteristics
MOTOROLA
MPC801 USER’S MANUAL
20-3
20
Solving equations (1) and (2) for K gives
K =
P
D
(T
A
+ 273
∞
C) + q
JA
P
D
2
(3)
where K is a constant pertaining to the particular part. K can be determined from equation
(3) by measuring P
and T
J
can be obtained by solving equations (1) and (2) iteratively for any value of T
(at equilibrium) for a known T
. Using this value of K
,
the values of P
D
A
.
20.3.1 Layout Practices
Each V
CC
pin on the MPC801 should be provided with a low-impedance path to the board’s
supply. Each GND pin should likewise be provided with a low-impedance path to ground.
The power supply pins drive distinct groups of logic on chip. The V
be bypassed to ground using at least four 0.1
μ
possible to the four sides of the package. The capacitor leads and associated printed circuit
traces connecting to chip V
CC
and GND should be kept to less than half an inch per capacitor
lead. A four-layer board is recommended, employing two inner layers as V
planes.
CC
power supply should
F by-pass capacitors located as close as
CC
and GND
All output pins on the MPC801 have fast rise and fall times. Printed circuit (PC) trace
interconnection length should be minimized in order to minimize undershoot and reflections
caused by these fast output switching times. This recommendation particularly applies to the
address and data busses. Maximum PC trace lengths of six inches are recommended.
Capacitance calculations should consider all device loads as well as parasitic capacitances
due to the PC traces. Attention to proper PCB layout and bypassing becomes especially
critical in systems with higher capacitive loads because these loads create higher transient
currents in the V
CC
and GND circuits. Pull up all unused inputs or signals that will be inputs
during reset. Special care should be taken to minimize the noise levels on the PLL supply
pins.