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Applications
MOTOROLA
MPC801 USER’S MANUAL
B-29
B
The memory controller can alter the cycle length and timing characteristics by configuring
the option and base registers parameters. To determine actual values, a timing analysis of
the interface is required. Figure B-2 illustrates a fast termination read cycle. This shows an
access with no compromise in the timings. Notice that the memory controller asserts the CS
from the rising edge of the SO and the PowerQUICC does not sample the data for two full
clock cycles. This means that the access times required by SRAMs are greatly reduced in
comparison to standard interfaces.
If a system contains slow peripherals with long data hold times, contention could occur on
the data bus between back-to-back cycles. By setting the ACS[0:1] or CSNT bits in the
option register, the CS signal can be delayed by a quarter or half a clock. Similarly, if the
CSNT bit is set, the CS and WE signals are negated a quarter of a clock earlier. However,
in this example it is assumed this is not the case and the ACS[0:1] bits are set to 00 and
CSNT is cleared. In an MPC801 design there are three critical timings for a fast termination
read cycle—SRAM enable access time (tACS), address access time (tAA), and output
enable time(tOE). The equation below provides a calculation of tACS:
tACS =2 tcyc – t18 – t22
Where,
tcyc = Period of processor clock = 40ns for a 25MHz clock
t22 = CLKOUT high to CS = 0-20ns
t18 = Data-in to CLKOUT high (data setup) = 6ns
Therefore,
tACS = 80ns – 6ns – 20ns
tACS = 54ns
Now the address access time (tAA) can also be calculated in a similar manner:
tAA = 2 tcyc – t18 – t8
Where, t8 = CLKOUT high to address valid 19ns.
Therefore,
tAA = 80ns – 6ns – 19ns
tAA = 55ns
Finally, the output enable time (tOE) is calculated as tOE = tcyc – t18 – t25.
Where,
t25 = CLKOUT high to OE asserted 11ns
tOE = 40ns – 6ns – 11ns
tOE = 23ns