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Electrical Characteristics

MPC801 USER’S MANUAL

Figure 20-1. External Clock Timing Diagram

A(6:31) To BS Valid–As Requested By Control Bit

BST2 In The Corresponding Word In The UPM

A(6:31) To GPL Valid–As Requested By Control Bit

GxT4 In The Corresponding Word In The UPM

UPWAIT Valid To CLKOUT Falling Edge

CLKOUT Falling Edge To UPWAIT Valid

AS Valid To CLKOUT Rising Edge

A(6:31), TSIZ(0:1), RD/WR, BURST, Valid To

CLKOUT Rising Edge

TS Valid To CLKOUT Rising Edge (Setup Time)

CLKOUT Rising Edge To TS Valid (Hold Time)

AS Negation To Memory Controller Signals

The timing for BR output is relevant when the MPC801 is selected to operate with an external bus arbiter.

The timing for BG output is relevant when the MPC801 is selected to operate with an internal bus arbiter.

The setup times required for TA, TEA and BI are relevant only when they are supplied by an external device and not when the

memory controller drives them.

The timing required for BR input is relevant when the MPC801 is selected to operate with an internal bus arbiter.

The timing for BG input is relevant when the MPB801 is selected to operate with an external bus arbiter.

The D[0:31] and DP[0:3] input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TAinput signal is

The D[0:31] and DP[0:3] input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only under

the control of the UPM in the memory controller.

The timing B30 refers to CS when ACS = ‘00’ and to WE[0:3] when CSNT = ‘0’.

The UPWAIT signal is considered asynchronous to the CLKOUT and is synchronized internally. The timings specified in B37

and B38 are specified to enable the freeze of the UPM output signals.

The AS signal is considered asynchronous to the CLKOUT. The B39 timing is specified to allow the behavior illustrated in

Figure 8-18.

Table 20-1. Bus Operation Timing (Continued)

CHARACTERISTIC

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