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TABLE OF CONTENTS (Continued)
Paragraph
Number
Page
Number
Title
MOTOROLA
MPC801 USER’S MANUAL
xi
Section 11
Memory Management Unit
11.1
11.2
11.2.1
11.3
11.4
11.4.1
11.4.2
11.5
11.5.1
11.5.2
11.6
11.6.1
11.6.1.1
11.6.1.2
11.6.1.3
11.6.1.4
11.6.1.5
11.6.2
11.6.2.1
11.6.2.2
11.6.2.3
11.6.2.4
11.6.2.5
11.6.2.6
11.6.2.7
11.6.2.8
11.6.3
11.6.3.1
11.6.3.2
11.6.3.3
11.6.4
11.6.4.1
11.6.4.2
11.6.4.3
11.7
11.7.1
11.7.2
11.7.3
11.7.4
Features .............................................................................................11-1
Address Translation ...........................................................................11-2
Translation Lookaside Buffer Operation ...................................11-2
Protection ...........................................................................................11-3
Storage Attributes ...............................................................................11-4
Reference and Change Bit Updates .........................................11-4
Storage Control ........................................................................11-4
Translation Table Structure ................................................................11-4
Level One Descriptor ................................................................11-8
Level Two Descriptor ................................................................11-9
Memory Management Unit Programming Model ..............................11-10
Configuration Registers ..........................................................11-10
Instruction MMU Control Register ...............................11-10
MI_AP Register ...........................................................11-11
Data MMU Control Register ........................................11-12
MD_AP Register .........................................................11-13
CASID Register ..........................................................11-14
Tablewalk Registers ...............................................................11-14
M_TWB Register ........................................................11-14
M_TW Register ...........................................................11-15
MI_EPN Register ........................................................11-15
MI_TWC Register .......................................................11-16
MI_RPN Register ........................................................11-17
MD_EPN Register ......................................................11-18
Data MMU Tablewalk Control Register ......................11-19
MD_RPN Register ......................................................11-20
Instruction Debug Registers ...................................................11-22
MI_DCAM Register .....................................................11-22
MI_DRAM0 Register ...................................................11-23
MI_DRAM1 Register ...................................................11-24
Data Debug Registers ............................................................11-25
MD_DCAM Register ...................................................11-25
MD_DRAM0 Register .................................................11-26
MD_DRAM1 Register .................................................11-27
Interrupts ..........................................................................................11-29
Implementation Specific Instruction TLB Miss ........................11-29
Implementation Specific Data TLB Miss .................................11-29
Implementation Specific Instruction TLB Error .......................11-29
Implementation Specific Data TLB Error ................................11-29