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Development Support
MOTOROLA
MPC801 USER’S MANUAL
18-53
18
DTLBER—Implementation Specific Data TLB Error
This bit is set as a result of an data TLB error. Results in debug mode entry if debug mode
is enabled and the corresponding enable bit is set.
Bits 22–27—Reserved
These bits are reserved and should be set to 0.
LBRK—Load/Store Breakpoint Interrupt
This bit is set as a result of the assertion of an load/store breakpoint. Results in debug mode
entry if debug mode is enabled and the corresponding enable bit is set.
IBRK—Instruction Breakpoint Interrupt
This bit is set as a result of the assertion of an instruction breakpoint. Results in debug mode
entry if debug mode is enabled and the corresponding enable bit is set.
EBRK—External Breakpoint Interrupt
This bit is set as a result of the assertion of an external breakpoint. Results in debug mode
entry if debug mode is enabled and the corresponding enable bit is set.
DPI—Development Port Interrupt
This bit is set by the development port as a result of a debug station nonmaskable request
or when entering debug mode immediately out of reset. Results in debug mode entry if
debug mode is enabled and the corresponding enable bit is set.
The reason for entering debug mode is provided by the interrupt cause register. All bits are
set by the hardware, cleared when the register is read, and cleared to zero when exiting
reset. Any attempt to write to this register is ignored.
18.5.3.2 DEBUG ENABLE REGISTER.
This register has a reset value of 0x2002000.
Bits 0, 4, and 5—Reserved
These bits are reserved and should be set to 0.
RSTE—Reset Interrupt Enable
0 = Debug mode entry is disabled (reset value).
1 = Debug mode entry is enabled.
DER
BIT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FIELD
RES
RSTE
CHSTP
E
MCIE
RESERVED
EXTIE
ALIE
PRIE
FPUVI
E
DECIE
RESERVED
SYSIE
TRE
RES
BIT
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
FIELD
RES
SEIE
ITLBMS
E
ITLBER
E
DTLBMS
E
DTLBER
E
RESERVED
LBRKE
IBRKE
EBRKE
DPIE