
CONTENTS
Paragraph
Number
Title
Page
Number
Contents
xi
10.5.3.5
10.5.3.6
10.5.3.7
MMU Status Register (MMUSR)........................................................... 10-14
MMU Fault, Test, or TLB Address Register (MMUAR)....................... 10-15
MMU Read/Write Tag and Data Entry Registers
(MMUTR and MMUDR) 10-15
MMU TLB.................................................................................................. 10-17
MMU Operation ......................................................................................... 10-18
MMU Implementation.................................................................................... 10-19
TLB Address Fields.................................................................................... 10-20
TLB Replacement Algorithm ..................................................................... 10-20
TLB Locked Entries.................................................................................... 10-21
MMU Instructions........................................................................................... 10-22
10.5.4
10.5.5
10.6
10.6.1
10.6.2
10.6.3
10.7
Chapter 11
Debug Support
11.1
11.2
11.2.1
11.3
11.3.1
11.3.2
11.3.3
11.4
11.4.1
11.4.2
11.4.3
11.4.4
11.4.5
11.4.6
11.4.7
Overview........................................................................................................... 11-1
Signal Descriptions........................................................................................... 11-3
Processor Status/Debug Data (PSTDDATA[7:0]) ....................................... 11-4
Real-Time Trace Support.................................................................................. 11-5
Begin Execution of Taken Branch (PST = 0x5)........................................... 11-8
Processor Stopped or Breakpoint State Change (PST = 0xE)................... 11-9
Processor Halted (PST = 0xF)...................................................................... 11-9
Programming Model....................................................................................... 11-10
Revision A Shared Debug Resources......................................................... 11-13
Address Attribute Trigger Registers (AATR, AATR1).............................. 11-13
Address Breakpoint Registers (ABLR/ABLR1, ABHR/ABHR1).......... 11-15
BDM Address Attribute Register (BAAR)................................................. 11-16
Configuration/Status Register (CSR).......................................................... 11-17
Data Breakpoint/Mask Registers (DBR/DBR1, DBMR/DBMR1) ......... 11-19
Program Counter Breakpoint/Mask Registers
(PBR, PBR1, PBR2, PBR3, PBMR) 11-20
Trigger Definition Register (TDR)............................................................. 11-21
Extended Trigger Definition Register (XTDR).......................................... 11-23
Resulting Set of Possible Trigger Combinations.................................... 11-25
PC Breakpoint ASID Control Register (PBAC)......................................... 11-26
PC Breakpoint ASID Register (PBASID).................................................. 11-26
Background Debug Mode (BDM).................................................................. 11-27
CPU Halt..................................................................................................... 11-28
BDM Serial Interface.................................................................................. 11-29
Receive Packet Format........................................................................... 11-30
Transmit Packet Format.......................................................................... 11-31
BDM Command Set.................................................................................... 11-32
11.4.8
11.4.9
11.4.9.1
11.4.10
11.4.11
11.5
11.5.1
11.5.2
11.5.2.1
11.5.2.2
11.5.3
F
Freescale Semiconductor, Inc.
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