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4-8
ColdFire CF4e Core User’s Manual
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FPU Programmer’s Model
4.3.1 Floating-Point Data Registers (FP0–FP7)
Floating-point data registers are analogous to the integer data registers for the
68K/ColdFire family. They always contain numbers in double-precision format, even
though the operand may be a single-precision value used in a single-precision calculation.
All external operands, regardless of the source data format, are converted to
double-precision format before being used in any calculation or being stored in a
floating-point data register. A reset or a null-restore operation sets FP0–FP7 to positive,
nonsignaling NANs.
4.3.1.1 Floating-Point Control Register (FPCR)
The FPCR, Figure 4-9, contains an exception enable byte (EE) and a mode control byte
(MC). The user can read or write to FPCR using FMOVE or FRESTORE. A processor
reset or a restore operation of the null state clears the FPCR. When this register is cleared,
the FPU never generates exceptions.
Figure 4-9. Floating-Point Control Register (FPCR)
Table 4-4 describes FPCR fields.
31
16
15
14
13
12
11
10
9
8
7
6
5
4
3
0
Field
—
BSUN INAN OPERR OVFL UNFL DZ INEX IDE — PREC RND
—
Reset
All zeros
R/W
R/W
Table 4-4. FPCR Field Descriptions
Bits
Field
Description
31–16
—
Reserved, should be cleared.
15–8
EE
Exception enable byte. Each EE bit corresponds to a floating-point exception class. The user can
separately enable traps for each class of floating-point exceptions.
15
BSUN
Branch set on unordered
14
INAN
Input not-a-number
13
OPERR
Operand error
12
OVFL
Overflow
11
UNFL
Underflow
10
DZ
Divide by zero
9
INEX
Inexact operation
8
IDE
Input denormalized
Exception Enable Byte (EE)
Mode Control Byte (MC)
F
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