Chapter 4. Floating-Point Unit (FPU)
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4-29
Instructions
Table 4-24 defines the terminology used in Table 4-23.
FSUB
1 1 1 1 0 0 1 0 0 0
EA
MODE
EA
REG
0
R
/
M
0
SRC
SPEC DEST
REG
OPMODE
FTST
1 1 1 1 0 0 1 0 0 0
EA
MODE
EA
REG
0
R
/
M
0
SRC
SPEC DEST
REG
0 1 1 1 0 1 0
Table 4-24. Instruction Format Terminology
Term
Definition
Instructions
Instructions appear in memory as sequential, 16-bit values, and are read in the above table left to
right. An instruction can have from 1 to 3 16-bit words. A shaded block indicates this word is never
used and is not present.
EA MODE
EA REG
Defines the effective address for an operand located external to the FPU. For most FPU instructions,
this field defines the location of an external source operand; for FP store operations, it specifies the
destination location.
R/M
If R/M = 0, an FPU data register is one source operand, otherwise the source operand is specified by
the EA {MODE, REG} fields.
SRC SPEC
Defines the format (byte, word, longword, single-, or double-precision) of an external operand.
DEST REG
Specifies the destination FPU data register.
COND
PREDICATE
Defines the condition to be evaluated (EQ, NE, and so on) during the execution of the FPU
conditional branch instruction.
OPMODE
Defines the exact operation to be performed by the FPU.
SZ
Defines the length of the PC-relative displacement for the FPU conditional branch instruction. If SZ =
0, the displacement is 16 bits, otherwise a 32-bit displacement is used.
dr
Specifies direction of the MOVE transfer. As a 0, it moves from memory to the FP; as 1, it moves from
the FP to memory.
REGISTER
LIST
Defines FPU data registers to be moved during the execution of the FMOVEM instruction.
REG SEL
Indicates the FPU control register to be moved during execution of an FMOVE control register
instruction.
Table 4-23. Floating-Point Instruction Formats (Continued)
Mnemonic
Instruction Code
F
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n
.