6-12
ColdFire CF4e Core User’s Manual
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Operand Execution Pipeline (OEP)
If an instruction changes an ExComputeEngine register that the next instruction uses
as an index register as an OagComputeEngine input with a scale factor of 1 (Xi.l), a
2-cycle pipeline stall occurs.
If an instruction changes a register from either OagComputeEngine or
ExComputeEngine and the next instruction uses that register as an index register
with a scale factor other than 1 (for example, Xi.l*{2,4,8}) as an input to
OagComputeEngine, a 3-cycle stall occurs. The case is shown in Figure 6-3.
The first three stalls are minimized by using ExComputeEngine-to-DS stage forwarding
logic shown on the OEP block diagrams. For register-busy conditions involving index
registers with scale factors not equal to one, the register file must be updated at the
completion of the EX stage before the stalled instruction can continue.
Intervening instructions can reduce or eliminate the stall, as in the following sequence:
add.l (d16,a7),a0
mov.l (a0),d0
This sequence represents the first type of change/use pipeline stall (three cycles) on register
A0. If instruction scheduling can be applied, the stall can be reduced or eliminated.
add.l (d16,a7),a0
op1 Ry,Rx
op2 Rw,Rz
mov.l (a0),d0
By inserting single-cycle instructions, op1 and op2, mov.l stalls only 1 cycle because the
3-cycle hazard is reduced by the 2 cycles during which op1 and op2 execute. A third
single-cycle instruction would eliminate the stall.
The instructions in Table 6-3 prevent stalls by using register renaming logic to make
destination register results available to subsequent instructions. These instructions are
unconditionally executed in OagComputeEngine.
Table 6-3. Instructions that Make Results Available to Subsequent Instructions
Instruction
<op> (Ay)+,Rx
<op> -(Ay),Rx
<op> Ry,(Ax)+
<op> Ry,-(Ax)
clr.l dx
lea <ea>y,Ax
mov.l #imm,Rx
mov.w #imm,Ax
mov3q.l #qimm,Rx
moveq #imm,Dx
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