12-2
ColdFire CF4e Core User’s Manual
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Scan Chains
We recommend using full-scan, multiplexed, D flip-flop methodology on the CF4e
implementation.
The CF4e core has one clock domain. The core has an optional test boundary (or test
wrapper) comprised of wrapper cells used to access all functional input and output ports.
The core has a BIST controller to BIST-test memory arrays attached to the core. The
processor-local memories are external to the CF4e design to allow the system designer to
configure and size those memories for a given application.
12.1 Scan Chains
This section describes the core and wrapper scan chains.
12.1.1 Core Scan Chains
Customers can choose the number of scan chains in the CF4e. Table 12-1 describes the test
ports of these scan chains.
12.1.2 Wrapper Scan Chains
Because scan is part of the implementation phase, the soft CF4e does not contain the test
wrapper in its RTL code when it is delivered to customers. However, a test wrapper can be
optionally created using synthesis scripts. Table 12.2 gives a more detailed description of
the test wrapper. If the test wrapper is used, customers can choose the number of wrapper
scan chains. An input wrapper chain has cells connected only to functional input ports of
the core. An output wrapper chain has cells connected only to functional output ports of the
core. The CF4e has no I/O or three-state ports. There are no wrapper cells on the clock
(clkfast), memory, scan input, or scan output ports of the cores. Table 12-2 describes the
test ports of the wrapper scan chains.
Table 12-1. CF4e Core Scan Chains
Scan Inputs
Scan Outputs
Scan Enable
Clock
si[N–1:0]
1
1
N represents the number of core scan chains
so[N-1:0]
1
se
clkfast
Table 12-2. CF4e Wrapper Scan Chains
Signal Types
Port Names
Wrapper scan data inputs
tbsi[K-1:0]
1
Wrapper scan data outputs
tbso[K-1:0]
1
Input wrapper scan enable
tbsei
Output wrapper scan enable
tbseo
Clock for wrapper scan chains
clkfast
F
Freescale Semiconductor, Inc.
n
.