
Chapter 1. Introduction
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1-5
Programming Model
protocol details of the external bus can vary widely, depending on system requirements.
The V4 design allows a core to operate at any integer multiplier (n = 1, 2, 3,...) faster than
the rest of the design. For multiple clock domains, the boundary is the M-Bus; that is, the
processor complex operates at the higher frequency, while the M-Bus and the rest of the
microprocessor operate at the slower speed. This well-defined, easy-to-use clock boundary
simplifies interface design and timing and eases production test complications.
The overall ColdFire implementation strategy of 100% synthesizable designs and use of
compiled memory arrays coupled with the modular system architecture allows easy
migration to any process technology and provides cost-effective integration capabilities
while targeting a variety of operating voltages and frequencies.
1.5 Programming Model
Figure 1-3 shows the V4 programming model, which is organized as follows:
User mode. User-mode software is restricted to user-mode instructions and registers.
Supervisor mode. Supervisor-mode software can reference all user- and
supervisor-mode instructions and registers.
The status register supervisor bit (SR[S]) selects the mode. Note that this figure shows
optional V4 registers implemented in the CF4e.
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