![](http://datasheet.mmic.net.cn/230000/V4ECFUM_datasheet_15625205/V4ECFUM_216.png)
9-2
ColdFire CF4E Core User’s Manual
For More Information On This Product,
Go to: www.freescale.com
CF4e Pin Characteristics
9.2 CF4e Pin Characteristics
Table 9-1 provides CF4e core pin characteristics. Most M-Bus and debug input signals are
driven directly into input capture registers in the CF4e core. K-Bus memories are specified
as synchronous; CF4e core outputs are next-state values registered in the memory device.
NOTE:
The letter ‘b’ at the end of a name indicates an active-low
signal.
Table 9-1. CF4e Pin Characteristics
No.
Type
Name
Bus Width
1
Description
M-Bus Outputs
1
Output
maddr
[31:0]
M-Bus address
2
Output
mtt
[1:0]
M-Bus transfer type
3
Output
mtm
[2:0]
M-Bus transfer modifier
4
Output
mrwb
—
M-Bus read/write
5
Output
msiz
[1:0]
M-Bus transfer size
6
Output
mwdata
[31:0]
M-Bus write data
7
Output
mwdataoe
—
M-Bus output enable
8
Output
mapb
—
M-Bus address phase
9
Output
mdpb
—
M-Bus data phase
10
Output
mlockb
—
M-Bus locked access
Debug Outputs
11
Output
bdmforceackb
—
BDM force M-Bus acknowledge
12
Output
cpustopb
—
Processor is stopped
13
Output
cpuhaltb
—
Processor is halted
14
Output
pstclk
—
PST/DDATA clock
Test Outputs
15
Output
so
[42:0]
Core parallel scan outputs
16
Output
tbso
[7:0]
Test boundary scan outputs
17
Output
bistdone
—
BIST done indicator
18
Output
bistdata
3:0]
BIST bitmap data
19
Output
bistfail
—
BIST memory failure indicator
20
Output
bisthold
—
BIST holding indicator
Outputs to K-Bus Memories
21
Output
nsientb
—
Next-state I-cache tag enable
22
Output
nsiwrttb
—
Next-state I-cache tag write
23
Output
nsiwlvt
[3:0]
Next-state I-cache tag write level
F
Freescale Semiconductor, Inc.
n
.