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| 型號(hào)： | V4ECFUM |
| 英文描述： | ColdFire CF4e Core User＇s Manual |
| 中文描述： | 核心的ColdFire CF4e用戶手冊(cè) |
| 文件頁(yè)數(shù)： | 152/372頁(yè) |
| 文件大?。?/td> | 4286K |
| 代理商： | V4ECFUM |
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7-6
ColdFire CF4E Core User’s Guide
For More Information On This Product,
Go to: www.freescale.com
Processor Exceptions
Table 7-3. Exceptions
Type
Description
Access error
If the MMU is disabled, access errors are reported only in conjunction with an attempted store to
write-protected memory. Thus, access errors associated with instruction fetch or operand read
accesses are not possible. The Version 4 processor, unlike the Version 2 and 3 processors, updates
the condition code register if a write-protect error occurs during a CLR or MOV3Q operation to
memory.
K-Bus accesses that fault (that is, terminated with a K-Bus transfer error acknowledge) generate an
access error exception. MMU TLB misses and access violations use the same fault. If the MMU is
enabled, all TLB misses and protection violations generate an access error exception. To determine if
a fault is due to a TLB miss or another type of access error, new FS encodings (described in
Table 7-2) signal TLB misses on the following:
Instruction fetch
Instruction extension fetch
Data read
Data write
Address error
An address error is caused by an attempted execution transferring control to an odd instruction
address (that is, if bit 0 of the target address is set), an attempted use of a word-sized index register
(Xi.w) or by an attempted execution of an instruction with a full-format indexed addressing mode.
If an address error occurs on a JSR instruction, the Version 4 processor first pushes the return
address onto the stack and then calculates the target address.
On Version 2 and 3 processors, the target address is calculated then the return address is pushed on
stack. If an address error occurs on an RTS instruction, the Version 4 processor preserves the
original return PC and writes the exception stack frame above this value. On Version 2 and 3
processors, the faulting return PC is overwritten by the address error stack frame.
Illegal
instruction
The scope of illegal instruction detection is implementation-specific across the generations of
ColdFire cores. For the CF4e core, the complete 16-bit opcode is decoded and this exception is
generated if execution of an unsupported instruction is attempted. Additionally, attempting to execute
an illegal line A or line F opcode generates unique exception types: vectors 10 and 11, respectively.
ColdFire processors do not provide illegal instruction detection on extension words of any instruction,
including MOVEC. Attempting to execute an instruction with an illegal extension word causes
undefined results.
Divide-by-zero
Attempting to divide by zero causes an exception (vector 5, offset = 0x014).
Privilege
violation
Caused by attempted execution of a supervisor mode instruction while in user mode. The
ColdFire
Programmer’s Reference Manual
lists supervisor- and user-mode instructions.
Trace exception
Trace mode, which allows instruction-by-instruction tracing, is enabled by setting SR[T].
If SR[T] is set, instruction completion (for all but the STOP instruction) signals a trace exception.The
STOP instruction has the following effects:
1 The instruction before the STOP executes and then generates a trace exception. In the exception
stack frame, the PC points to the STOP opcode.
2 When the trace handler is exited, the STOP instruction is executed, loading the SR with the
immediate operand from the instruction.
3 The processor then generates a trace exception. The PC in the exception stack frame points to the
instruction after STOP, and the SR reflects the value loaded in the previous step.
If the processor is not in trace mode and executes a STOP instruction where the immediate operand
sets SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack
frame points to the instruction after STOP, and the SR reflects the value loaded in step 2. Note that
because ColdFire processors do not support hardware stacking of multiple exceptions, it is the
responsibility of the operating system to check for trace mode after processing other exception types.
For example, when a TRAP instruction executes in trace mode, the processor initiates the TRAP
exception and passes control to the corresponding handler. If the system requires a trace exception,
the TRAP exception handler must check for this condition (SR[15] in the exception stack frame set)
and pass control to the trace handler before returning from the original exception.
F
Freescale Semiconductor, Inc.
n
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