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ColdFire CF4e Core User’s Manual
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Cache Overview
The ColdFire processor or an external emulator using the debug module can perform these
initialization functions.
8.6.4 Programming ROMBARs for Power Management
Depending on the ROMBAR configuration, memory accesses can be sent to a ROM
module and cache simultaneously. If an access hits both, the ROM module sources read
data and the instruction cache access is discarded. Because the ROM contains only data,
setting ROMBAR[SC,UC] lowers power dissipation by disabling the ROM during
instruction fetches.
Table 8-26 shows typical ROMBAR settings:
.
RAMBARs are configured similarly, as described in Section 8.5.5, “Programming
RAMBARs for Power Management.”
8.7 Cache Overview
This section describes the Harvard cache implementation, including organization,
configuration, and coherency. It describes cache operations and how the instruction and
data caches interact with other memory structures.
The CF4e implements a special branch instruction cache for accelerating branches, enabled
by a bit in the cache access control register (CACR[BEC]).
Caches improve system performance by providing single-cycle access to the instruction
and data pipelines. This decouples processor performance from system memory
performance, increasing bus availability for on-chip DMA or external devices. Figure 8-1
and Figure 8-2 show the integration of the instruction and data caches in the local memory
model.
Table 8-26. Examples of Typical ROMBAR Settings
ROMBAR[7–0]
Data Contained in ROM
0x21
Both code and data
0x2B
Code only
0x35
Data only
0x35
Supervisor and user data
0x37
Supervisor-only data
0x3C
User-only data
0xAB
Supervisor and user code
0xAF
Supervisor-only code
0xBB
User-only code
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