A-4
ColdFire CF4e Core User’s Manual
For More Information On This Product,
Go to: www.freescale.com
set_input_delay { 0.00 } -clock “VCLK” find(port,”icsize[*]”)
set_input_delay { 0.00 } -clock “VCLK” find(port,”ocsize[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”ictag3do[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”icw3do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”icv3do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”ictag2do[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”icw2do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”icv2do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”ictag1do[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”icw1do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”icv1do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”ictag0do[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”icw0do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”icv0do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.66 ) } -clock “VCLK”
find(port,”iclvl3do[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.66 ) } -clock “VCLK”
find(port,”iclvl2do[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.66 ) } -clock “VCLK”
find(port,”iclvl1do[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.66 ) } -clock “VCLK”
find(port,”iclvl0do[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”octag3do[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”ocw3do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”ocv3do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”octag2do[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”ocw2do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”ocv2do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”octag1do[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”ocw1do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”ocv1do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”octag0do[*]”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”ocw0do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.50 ) } -clock “VCLK”
find(port,”ocv0do”)
set_input_delay { REGDELAY + ( clk_logic_period * 0.66 ) } -clock “VCLK”
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Freescale Semiconductor, Inc.
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