
Chapter 2. Registers
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Supervisor Programming Model
Figure 2-5. Floating-Point Programmer’s Model
The programmer’s model for the FPU consists of the following:
Eight 64-bit floating-point data registers (FP0–FP7)
One 32-bit floating-point control register (FPCR)
One 32-bit floating-point status register (FPSR)
One 32-bit floating-point instruction address register (FPIAR)
These registers are described in Section 4.3, “FPU Programmer’s Model.”
2.3 Supervisor Programming Model
Typically, system programmers use the supervisor programming model to implement
operating system functions and provide memory and I/O control. The CF4e supervisor
programming model provides access to user registers and additional supervisor registers,
which include the upper byte of the status register (SR), the supervisor stack pointer (SSP),
the vector base register (VBR), and registers for configuring attributes of the address space
connected to the processor core. Most supervisor-level registers are accessed by using the
MOVEC instruction with the control register definitions in Table 2-4.
Figure 2-6 shows the supervisor programming model.
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0
FP0
FP1
FP2
FP3
FP4
FP5
FP6
FP7
FPCR
FPSR
FPIAR
Floating-point data registers
Floating-point control register
Floating-point status register
Floating-point instruction address register
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