
Chapter 8. Local Memory
For More Information On This Product,
Go to: www.freescale.com
8-15
Local Memory Connection Specification
All instruction cache data arrays are 32 bits wide. The nsicwrdata[31:0] signals are the data
array input data and iclvl0do[31:0], iclvl1do[31:0], clvl2do[31:0], and iclvl3do[31:0] are
the data array output data for all sizes and levels of instruction cache.
All instruction cache tag arrays are 24 bits wide. The nsiaddrt[31:9] signals are the tag array
input data and ictag3do[31:9], ictag2do[31:9], ictag1do[31:9], and ictag0do[31:9] are the
tag array output data for all sizes of instruction cache.
The nsirowst[9:0] signals the array address for the tag arrays. The nsirowsd[11:0] signals
are the array address for the data arrays. The instruction cache controller provides enough
address bits for the largest supported cache sizes.
The array address is connected as shown in Table 8-12 for all supported instruction cache
data array sizes:
Output
nsisv
Next-state instruction cache tag valid bit
Output
nsiendb
Next-state instruction cache data enable
Output
nsiwrtdb
[3:0]
Next-state instruction cache data write level
Output
nsiwtbyted
[3:0]
Next-state instruction cache data byte write
Output
nsirowsd
[11:0]
Next-state instruction cache data address
Output
nsicwrdata
[31:0]
Next-state instruction cache write data
Input
ictag3do
[31:9]
Instruction cache level 3 tag data output
Input
icw3do
Instruction cache level 3 written bit output
Input
icv3do
Instruction cache level 3 valid bit output
Input
ictag2do
[31:9]
Instruction cache level 2 tag data output
Input
icw2do
Instruction cache level 2 written bit output
Input
icv2do
Instruction cache level 2 valid bit output
Input
ictag1do
[31:9]
Instruction cache level 1 tag data output
Input
icw1do
Instruction cache level 1 written bit output
Input
icv1do
Instruction cache level 1 valid bit output
Input
ictag0do
[31:9]
Instruction cache level 0 tag data output
Input
icw0do
Instruction cache level 0 written bit output
Input
icv0do
Instruction cache level 0 valid bit output
Input
iclvl3do
[31:0]
Instruction cache level 3 data output
Input
iclvl2do
[31:0]
Instruction cache level 2 data output
Input
iclvl1do
[31:0]
Instruction cache level 1 data output
Input
iclvl0do
[31:0]
Instruction cache level 0 data output
Table 8-11. Instruction Cache Memory Array Connections (Continued)
Direction/Size
Signal Name
Bus Width
Definition
F
Freescale Semiconductor, Inc.
n
.