
Chapter 8. Local Memory
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8-9
Local Memory Connection Specification
The signals in Table 8-3 connect a KRAM controller to its SRAM array.
KRAM memories are 32 bits wide. The kram0di[31:0] and kram1di[31:0] signals are the
array input data and kram0do[31:0] and kram1do[31:0] are the array output data for all
KRAM sizes.
The kram0addr[15:2] and kram1addr[15:2] signals are the array addresses. The KRAM
controller provides enough address bits for the largest-supported array sizes.
The 2 low-order address bits, which are not sourced from the KRAM controller to the
KRAM arrays directly, select the bytes in the 32-bit KRAM data array interface. For read
operations, the KRAM controller always fetches 32 bits and the controller sends this
information to the 32-bit K-Bus. The K-Bus data requester is responsible for using only the
bytes selected. The KRAM controller uses byte write enables to select bytes for write
operations.
Table 8-4 shows how the array address is connected for all supported KRAM array sizes.
Table 8-2. KRAM Size
kram{0,1}size[3:0]
Total Size
Configuration
0000
0 bytes
KRAM{0,1} disabled
0001
512 bytes
128 x 4 bytes
0010
1 Kbytes
256 X 4 bytes
0011
2 Kbytes
512 X 4 bytes
0100
4 Kbytes
1024 X 4 bytes
0101
8 Kbytes
2048 X 4 bytes
0110
16 Kbytes
4096 X 4 bytes
0111
32 Kbytes
8192 X 4 bytes
1000
64 Kbytes
16384 X 4 bytes
1001–1111
RFU
RFU
Table 8-3. KRAM Memory Array Connections
Direction/Size
Signal Name
Definition
output[15:2]
kram0addr
kram1addr
KRAM0 14-bit address
KRAM1 14-bit address
output[31:0]
kram0di
kram1di
KRAM0 32-bit data in
KRAM1 32-bit data in
output[3:0]
kram0web
kram1web
KRAM0 byte write enables (active-low)
KRAM1 byte write enables (active-low)
output
kram0csb
kram1csb
KRAM0 chip select (active-low)
KRAM1 chip select (active-low)
input[31:0]
kram0do
kram1do
KRAM0 32-bit data out
KRAM1 32-bit data out
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