
Chapter 1. Introduction
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1-13
Instruction Set Overview
alterable and data). ColdFire microprocessors support 12 of the most commonly used
M68000 Family effective addressing modes. Table 1-3 summarizes these modes.
1.9 Instruction Set Overview
The original ColdFire ISA was derived from M68000 Family opcodes based on extensive
analysis of embedded application code. After the first ColdFire compilers were created,
developers identified ISA additions that would enhance both code density and overall
performance. Additionally, as users implemented ColdFire-based designs into a wide range
of embedded systems, they identified frequently used instruction sequences that could be
improved by creating new instructions. This observation was especially prevalent in
environments that used substantial amounts of assembly language code.
The original ISA minimized support for instructions referencing byte and word operands.
MOVE.B and MOVE.W were fully supported; otherwise, only CLR (clear) and TST (test)
supported these data types. Based on input from compiler writers and system users, a set of
instruction enhancements was proposed to address the following:
Enhanced support for byte and word-sized operands through new move operations
Enhanced support for position-independent code
For descriptions of the ColdFire instruction set, see the latest version of the
ColdFire
Programmer’s Reference Manual
.
The following list summarizes new and enhanced instructions of ISA_B:
Table 1-3. ColdFire Effective Addressing Modes
Addressing Modes
Syntax
Mode
Field
Register
Field
Category
Data
Memory
Control
Alterable
Absolute data addressing
Short
Long
(xxx).W
(xxx).L
111
111
000
001
X
X
X
X
X
X
—
—
Address register indirect with scaled index
8-bit displacement
(d
8
, An, Xi*SF)
110
register no.
X
X
X
X
Immediate
#<xxx>
111
100
X
X
—
—
Program counter indirect
with displacement
(d
16
, PC)
111
010
X
X
X
—
Program counter indirect with scaled index
8-bit displacement
(d
8
, PC, Xi*SF)
111
011
X
X
X
—
Register direct
Data
Address
Dn
An
000
001
register no.
register no.
X
—
—
—
—
—
X
X
Register indirect
Address
Address with Postincrement
Address with Predecrement
Address with Displacement
(An)
(An)+
–(An)
(d
16
, An)
010
011
100
101
register no.
register no.
register no.
register no.
X
X
X
X
X
X
X
X
X
—
—
X
X
X
X
X
F
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n
.