
2-12
ColdFire CF4e Core User’s Manual
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Programming Model Table
The following example shows how to set the MBAR to location 0x1000_0000 using the D0
register. Setting MBAR[V] validates the MBAR location. This example assumes all
accesses are valid:
move.1 #0x10000001,D0
movec DO,MBAR
2.4 Programming Model Table
Table 2-4 lists register names, the CPU space location, whether the register is written from
the processor using the MOVEC instruction, and the complete register name.
6
AM
Alternate master mask. When AM = 0 and an alternate master (external master or DMA) accesses
MBAR-mapped registers, MBAR[SC,SD,UC,UD] are ignored in address decoding. These fields
mask address space, placing the MBAR-mapped register in a specific address space or spaces.
5
C/I
Mask CPU space and interrupt acknowledge cycles. Note that C/I must be set if BA = 0.
0 Activates the corresponding MBAR-mapped register
1 Regular external bus access
4
SC
Setting masks supervisor code space in MBAR address range
3
SD
Setting masks supervisor data space in MBAR address range
2
UC
Setting masks user code space in MBAR address range
1
UD
Setting masks user data space in MBAR address range
0
V
Valid. Determines whether MBAR settings are valid.
0 MBAR contents are invalid.
1 MBAR contents are valid.
Table 2-4. ColdFire CPU Registers
Name
CPU Space (Rc)
Written with MOVEC
Register Name
Memory Management Control Registers
CACR
0x002
Yes
Cache control register
ASID
0x003
Yes
Address space identifier
ACR0–ACR3
0x004–0x007
Yes
Access control registers 0–3
MMUBAR
0x008
Yes
MMU base address register
Processor General-Purpose Registers
D0–D7
0x(0,1)80–0x(0,1)87
No
Data registers 0–7 (0 = load, 1 = store)
A0–A7
0x(0,1)88–0x(0,1)8F
No
Address registers 0–7 (0 = load, 1 = store)
A7 is user stack pointer
Table 2-3. MBAR Field Descriptions (Continued)
Bits
Field
Description
F
Freescale Semiconductor, Inc.
n
.