
Chapter 6. Instruction Pipeline and Timing
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6-11
Operand Execution Pipeline (OEP)
provided by zero-cycle Bcc instructions, 33% of the dynamic instruction stream is executed
as pairs in the OEP.
Superscalar dispatch can be disabled for performance analysis. Setting CACR[17] disables
Bcc instruction folding. Setting CACR[0] disables OEP instruction folding on zero-cycle
move pairs. Both are enabled at reset.
6.3.3 Sequence-Related OEP Stalls
The most common sequence-related OEP stall is the change/use (register-busy) register
stall, which occurs when an instruction modifies a register in the ExComputeEngine that a
subsequent instruction needs as an OagComputeEngine input. The subsequent instruction
stalls in the DS stage until the register is updated. Consider the following:
lsl.l d1,d0
mov.l (d8,a0,d0.l*4),d1
In this sequence, shown in Figure 6-3, the 2-cycle mov.l instruction stalls waiting for lsl.l
to update the d0 index register. The mov.l instruction requires a second pipeline cycle to
calculate the three-component indexed operand address.
Figure 6-3. Sequence-Related OEP Sequence Stall
In Figure 6-3, mov.l cannot begin its second cycle of indexed operand address generation
until the preceding instruction update d0, causing a worst-case, 3-cycle stall.
The worst-case change/use register-busy stalls are summarized as follows:
If an instruction changes an ExComputeEngine base register (An) and the next
instruction uses that register as an OagComputeEngine input, a 3-cycle stall occurs.
If mov.l <mem>y,Ax loads a base register and the next instruction uses that register
as an OagComputeEngine input, a 2-cycle stall occurs. This sequence, common in
pointer manipulation, is optimized by adding a OC2-to-DS forwarding datapath.
lsl
lsl
lsl
lsl
lsl
mov
mov
mov
mov
Register d0
Old
New
mov
DS
OAG
OC1
OC2
EX
3-cycle regBusy stall
mov
Processor clock
F
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