Chapter 8. Local Memory
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8-51
Cache Overview
movec
move.l
movec
rts
d0,ACR1
#0x01000000,d0
d0,CACR
;ACR1 off
;Invalidate and disable cache
_cache_flush:
nop
moveq.l
moveq.l
move.l
;synchronize—flush store buffer
;initialize way counter
;initialize set counter
;initialize cpushl pointer
#0,d0
#0,d1
d0,a0
setloop:
cpushl
add.l
addq.l
cmpi.l
bne
dc,(a0)
#0x0010,a0
#1,d1
#128,d1
setloop
;push cache line a0
;increment set index by 1
;increment set counter
;are sets for this way done
moveq.l
addq.l
move.l
cmpi.l
bne
rts
#0,d1
#1,d0
d0,a0
#4,d0
setloop
;set counter to zero again
;increment to next way
;set = 0, way = d0
;flushed all the ways
The following CACR loads assume the instruction cache has been invalidated, the default
instruction cache mode is cacheable, and the default data cache mode is copyback.
dataCacheLoadAndLock:
move.l
movec
#0xA3080800,d0
d0,cacr
;enable and invalidate data cache ...
;... in the CACR
The following code preloads half of an 8-Kbyte data cache. It assumes a contiguous block
of data is to be mapped into the cache, starting at a 0-modulo-8K address.
move.l
lea
#256,d0
data_,a0
;256 16-byte lines in 4K space
;load pointer defining data area
dataCacheLoop:
tst.b
lea
subq.l
bne.b
(a0)
16(a0),a0
#1,d0
dataCacheLoop
;touch location + load into data cache
;increment address to next line
;decrement loop counter
;if done, then exit, else continue
;A 4-Kbyte region was loaded into levels 0 and 1 of the 8-Kbyte cache. Lock it!
move.l
movec
rts
#0xAA088000,d0
d0,cacr
;set the data cache lock bit ...
;... in the CACR
align
16
The following CACR loads assume the data cache has been invalidated, the default
instruction cache mode is cacheable, and the default operand cache mode is copyback.
Note that this function must be mapped into a cache inhibited or SRAM space or these text
lines will be prefetched into the instruction cache, which may displace some of the
16-Kbyte space being explicitly fetched.
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