Chapter 11. Debug Support
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11-15
Programming Model
11.4.3 Address Breakpoint Registers (ABLR/ABLR1,
ABHR/ABHR1)
The address breakpoint low and high registers (ABLR, ABLR1, ABHR, and ABHR1,
Figure 11-7), define regions in the processor’s data address space that can be used as part
of the trigger. These register values are compared with the address for each transfer on the
processor’s high-speed local bus. The trigger definition register (TDR) identifies the
trigger as one of three cases:
Identically the value in ABLR
Inside the range bound by ABLR and ABHR inclusive
Outside that same range
XTDR determines the same for ABLR1 and ABHR1.
Table 11-9 describes ABLR and ABLR1 fields.
2–0
TM
Transfer modifier. Compared with the local bus transfer modifier signals, which give
supplemental information for each transfer type.
TT = 00 (normal mode):
000 Data and instruction cache line push
001 User data access
010 User code access
011 Instruction cache invalidate
100 Data cache push/Instruction cache invalidate
101 Supervisor data access
110 Supervisor code access
111 INTOUCH instruction access
TT = 10 (emulator mode):
0xx–100 Reserved
101 Emulator mode data access
110 Emulator mode code access
111 Reserved
TT = 11 (acknowledge/CPU space transfers):
000 CPU space access
001–111 Interrupt acknowledge levels 1–7
These bits also define the TM encoding for BDM memory commands (for backward
compatibility).
31
0
Field
Address
Reset
—
R/W Write only. ABHR and ABHR1 are accessible in supervisor mode as debug control registers 0x0C and
0x1C, using the WDEBUG instruction and via the BDM port using the
RDMREG
and
WDMREG
commands.
ABLR and ABLR1 are accessible in supervisor mode as debug control register 0x0D and 0x1D, using the
WDEBUG instruction and via the BDM port using the
WDMREG
command.
DRc[4–0]
0x0D (ABLR); 0x1D (ABLR1); 0x0C (ABHR); 0x1C (ABHR1)
Figure 11-7. Address Breakpoint Registers (ABLR, ABHR, ABLR1, ABHR1)
Table 11-8. AATR and AATR1 Field Descriptions (Continued)
Bits
Name
Description
F
Freescale Semiconductor, Inc.
n
.