8-52
ColdFire CF4e Core User’s Manual
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Cache Overview
instructionCacheLoadAndLock:
move.l
movec
#0xa2088100,d0
d0,cacr
;enable and invalidate the instruction
;cache in the CACR
The following code segments preload half of a 16-Kbyte instruction cache. It assumes a
contiguous block of data is to be mapped, starting at a 0-modulo-8K address.
move.l
lea
#512,d0
code_,a0
;512 16-byte lines in 8K space
;load pointer defining code area
instCacheLoop:
;
intouch (a0)
;touch location + load into instruction cache
;Note in the assembler we use, there is no INTOUCH opcode. The following
;is used to produce the required binary representation
cpushl
#nc,(a0)
;touch location + load into
;instruction cache
;increment address to next line
;decrement loop counter
;if done, then exit, else continue
lea
subq.l
bne.b
16(a0),a0
#1,d0
instCacheLoop
;A 8K region was loaded into levels 0 and 1 of the 16-Kbyte instruction cache.
;lock it!
move.l
movec
rts
#0xa2088800,d0
d0,cacr
;set the instruction cache lock bit
;in the CACR
8.7.12 Cache Operation Summary
This section gives operational details for the cache and presents instruction and data
cache-line state diagrams.
8.7.13 Instruction Cache State Transitions
Because the instruction cache does not support writes, it supports fewer operations than the
data cache. As Figure 8-20 shows, an instruction cache line can be in one of two states, valid
or invalid. Modified state is not supported. Transitions are labeled with a capital letter
indicating the previous state and with a number indicating the specific case listed in
Table 8-30. These numbers correspond to the equivalent operations on data caches,
described in Section 8.7.13.1, “Data Cache State Transitions.”
Figure 8-20. Instruction Cache Line State Diagram
Valid
V = 1
II5—ICINVA
II6—CPUSHL & IDPI
II7—CPUSHL & IDPI
IV1—CPU read miss
IV2—CPU read hit
IV7—CPUSHL & IDPI
IV5—ICINVA
IV6—CPUSHL & IDPI
Invalid
V = 0
II1—CPU read miss
F
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