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Chapter 11. Debug Support
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11-9
Real-Time Trace Support
11.3.2 Processor Stopped or Breakpoint State Change
(PST = 0xE)
The 0xE encoding is generated either as a one- or multiple-cycle issue as follows:
When the core is stopped by a STOP instruction, this encoding appears in
multiple-cycle format. The ColdFire processor remains stopped until an interrupt
occurs; thus, PSTDDATA outputs display 0xE until stopped mode is exited.
When a breakpoint status change is to be output on PSTDDATA, 0xE is displayed
for one cycle, followed immediately with the 4-bit value of the current trigger
status, where the trigger status is left justified rather than in the CSR[BSTAT]
description. Section 11.4.5, “Configuration/Status Register (CSR),” shows that
status is right justified. That is, the displayed trigger status on PSTDDATA after a
single 0xE is as follows:
— 0x0 = no breakpoints enabled
— 0x2 = waiting for level-1 breakpoint
— 0x4 = level-1 breakpoint triggered
— 0xA = waiting for level-2 breakpoint
— 0xC = level-2 breakpoint triggered
Thus, 0xE can indicate multiple events, based on the next value, as Table 11-5 shows.
Table 11-5. 0xE Status Posting
11.3.3 Processor Halted (PST = 0xF)
PST is 0xF when the processor is halted (see Section 11.5.1, “CPU Halt”). Because this
encoding defines a multiple-cycle mode, the PSTDDATA outputs display 0xF until the
processor is restarted or reset. Therefore, PSTDDATA[7:0] continuously are 0xFF.
NOTE:
HALT can be distinguished from a data output 0xFF by
counting 0xFF occurrences on PSTDDATA. Because data
always follows a marker (0x8, 0x9, 0xA, or 0xB), the longest
occurrence in PSTDDATA of 0xFF in a data output is four.
Two scenarios exist for data 0xFFFF_FFFF:
PSTDDATA Stream Includes
Result
{0xE, 0x2}
Breakpoint state changed to waiting for level-1 trigger
{0xE, 0x4}
Breakpoint state changed to level-1 breakpoint triggered
{0xE, 0xA}
Breakpoint state changed to waiting for level-2 trigger
{0xE, 0xC}
Breakpoint state changed to level-2 breakpoint triggered
{0xE, 0xE}
Stopped mode.
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